5G Small Cell PCIe to JESD204B Bridge Reference Design

Data Transfer between PCIe IP and JESD204B IP Cores in a Duplex Direction

The 5G Small Cell PCIe to JESD204B bridge design supports data transfer between PCIe IP and JESD204B IP in a duplex direction. The design supports a 6.144 Gbps per lane of data transfer from JESD204B IP, embeds the data into PCIe Memory Write packet, and transmits the packet to PCIe link partner at Gen3 speed. Similarly, data transfer from the PCIe link partner is extracted from the PCIe Memory Read packet and forwarded to the JESD204B IP for transmission.

PCI Express is a high performance, fully scalable, well-defined standard for a wide variety of computing and communications platforms. Being a packet-based serial technology, PCI Express greatly reduces the number of required pins and simplifies board routing and manufacturing. Each PCI Express device has the advantage of full duplex communication with its link partner to greatly increase overall system bandwidth. A four-lane link has eight times the data rate in each direction of a conventional bus.

The JESD204B standard describes a multi-gigabit serial data link between converter(s) and a receiver, commonly a device such as an FPGA or ASIC. JESD204 is a high-speed serial interface designed to connect Analog to Digital Converter (ADCs) and Digital to Analog Converter (DACs) to logic devices.

PCIe TX/RX Engine and Memory Module - The design contains control and buffering logics to control data flow from PCIe domain to JESD204B domain and vice versa, ensuring data throughput is always maintained during operation.

SPI Interface - Configuration and status of the bridge as well as the IPs could be accessed externally through a SPI interface. Users could control the bring-up sequence, modify configuration and check the link status through this interface.


  • Support PCI Express IP in Gen3x4 Endpoint Mode
  • Connects to a JESD204B IP running at 6.144 Gbps x4 lanes
  • User clock domain support 250 MHz for PCIe and 153.6 MHz for JESD204B
  • Support interoperability with ADI for JESD204B
  • Control logic to ensure no starving of data throughput to JESD204B

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Block Diagram

Resource Utilization

Device Family Language Speed Grade Utilization (LUTs) fMAX (MHz) I/O Buffers Architecture Resources
CertusPro™-NX1 Verilog -9 3787 250 MHz 24 2 PLLs, 1 OSC

1. Performance and utilization characteristics are generated using LFCPNX-100-9LFG672C, with Lattice Radiant 2022.1 design software with Synplify Pro.