MDIO Leader IP Core

A Serial Bus Protocol to Configure the PHY Layer Transceiver Parameters

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The MDIO leader core is provided as an encrypted IP core. The diagram below shows the MDIO leader core functional block diagram. The user interface is provided as a simple APB/AHB/AXI-L compliant interface configurable by the HOST_INTERFACE parameter.

Latest Resource Utilization details are available in the IP Core User Guide.

Features

  • Implements the IEEE 802.3 Standard, Clause 22 and Clause 45 LEADER interface
  • Three different standard interfaces for accessing the control and status signals of Leader: APB, AHB-L and AXI-L. The interface selection is controlled using parameter.
  • User control for selection between Clause 22 and Clause 45 protocols.
  • Dynamic selection for Preamble pattern generation in MDIO frames.

Block Diagram

MDIO Leader IP Core Block DiagramExpand Image

Resource Utilization

LFCPNX-100
Interface PFU registers LUT-4
AHB-L 145 190
APB 136 185
AXI-L 185 240

Ordering Information

The MDIO Leader is provided at no additional cost with Lattice Radiant.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
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MDIO Leader IP User Guide
FPGA-IPUG-02223 1.1 12/20/2024 PDF 1.4 MB
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MDIO Leader IP Release Notes
FPGA-RN-02029 1.0 12/20/2024 PDF 206.6 KB

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