MDIO Leader IP Core

A Serial Bus Protocol to Configure the PHY Layer Transceiver Parameters

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The MDIO leader core is provided as an encrypted IP core. The diagram below shows the MDIO leader core functional block diagram. The user interface is provided as a simple APB/AHB/AXI-L compliant interface configurable by the HOST_INTERFACE parameter.

Latest Resource Utilization details are available in the IP Core User Guide.

Features

  • Implements the IEEE 802.3 Standard, Clause 22 and Clause 45 Leader interface.
  • Three different standard interfaces for accessing the control and status signals of Leader: APB, AHB-L, and AXI-L. The interface selection is controlled using parameter
  • User control for selection between Clause 22 and Clause 45 protocols.
  • Dynamic selection for Preamble pattern generation in MDIO frames.
  • User control for MDC clock divider settings.

Block Diagram

MDIO Leader IP Core Block Diagram放大图片

Ordering Information

The MDIO Leader is provided at no additional cost with Lattice Radiant.

Documentation

快速参考
资讯资源
标题 编号 版本 日期 格式 文件大小
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MDIO Leader IP Core - User Guide
FPGA-IPUG-02223 1.3 12/11/2025 PDF 1.4 MB
标题 编号 版本 日期 格式 文件大小
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MDIO Leader IP Core - Release Notes
FPGA-RN-02029 1.2 12/11/2025 PDF 251.3 KB

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