10 Gb Ethernet MAC & PCS Reference Design

10 Gb Ethernet MAC & PCS with Data Generator and Checker

The Lattice Semiconductor 10 Gb Ethernet MAC IP core supports the ability to transmit and receive data between a host processor and an Ethernet network. The main function of the 10 Gb Ethernet MAC is to ensure that the media access rules specified in the IEEE 802.3 standards are met while transmitting a frame of data over the Ethernet. On the receive side, the Ethernet MAC extracts the different components of a frame and transfers them to higher applications through an AXI4-Stream interface.

The 10 Gb Ethernet PCS IP core provides XGMII interface to MAC and follows IEEE 802.3 10GBASE-R standard. It supports 64-bit data and 8-bit control signals for both transmit and receive paths.

This reference design demonstrates an example of a 10GBASE-R application using a 10 Gb Ethernet MAC IP core with a 10 Gb Ethernet PCS IP core in loopback mode. A simple Ethernet packet generator is included to generate Ethernet packets to be transmitted on the transmitter (TX) and compare them with the received packets from the receiver (RX).


  • 10 Gb Ethernet MAC complying to IEEE 802.3
  • 10 Gb Ethernet PCS complying to IEEE 802.3 10G Base-R standard
  • Ethernet packet generator to generate and compare packets
  • Supports internal loopback (Near PMA Loopback) and external loopback mode
  • Supports CertusPro-NX FPGA

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Block Diagram

10 Gb Ethernet MAC & PCS Reference Design Block Diagram

Performance and Resource Utilization

Device Family Language Speed Grade Utilization (LUTS) fMAX (MHz) I/O Architecture Resources
CertusPro-NX1 Verilog -8 4690 >156.25 22 1 PLL, 1 PCS

1. Performance and utilization characteristics are generated using LFCPNX-100-8LFG672C, with Lattice Radiant® 3.1 design software with LSE (Lattice Synthesis Engine).
Note: The Maximum Clock Frequency is obtained by running the timing analysis with the Lattice design software. Timing simulation should be run after any changes are made and the reference design is merged with the overall design.


Technical Resources
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10Gb Ethernet MAC & PCS Reference Design – User Guide
FPGA-RD-02248 1.2 3/10/2024 PDF 1.9 MB
10Gb Ethernet MAC & PCS Reference Design – Source Code
3/11/2024 ZIP 11.2 MB

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