The Lattice Semiconductor 10 Gb Ethernet MAC IP core supports the ability to transmit and receive data between a host processor and an Ethernet network. The main function of the 10 Gb Ethernet MAC is to ensure that the media access rules specified in the IEEE 802.3 standards are met while transmitting a frame of data over the Ethernet. On the receive side, the Ethernet MAC extracts the different components of a frame and transfers them to higher applications through an AXI4-Stream interface.
The 10 Gb Ethernet PCS IP core provides XGMII interface to MAC and follows IEEE 802.3 10GBASE-R standard. It supports 64-bit data and 8-bit control signals for both transmit and receive paths.
This reference design demonstrates an example of a 10GBASE-R application using a 10 Gb Ethernet MAC IP core with a 10 Gb Ethernet PCS IP core in loopback mode. A simple Ethernet packet generator is included to generate Ethernet packets to be transmitted on the transmitter (TX) and compare them with the received packets from the receiver (RX).