The AXI4 Multi Port Bridge for Memory Controller (MPMC) IP connects multiple external managers to a single memory controller. This IP runs only on AXI4 and supports separate clock domains between each external managers and the subordinate.
Proper Clock Domain Crossing (CDC) Mechanism – Proper clock domain crossing (CDC) mechanism is in place to ensure proper clock domain crossing between the SI and MI blocks. There are no signals crossing between each SI block.
Internal Reset Synchronous Deassertion (RSD) Block – All resets have the deassertion edge synchronized to the respective clock edge with an internal reset synchronous deassertion (RSD) block.