Divider IP Core

A One-Clock Divider that Supports Configurable Output Latency

The Divider IP core uses a non-restoring division algorithm to implement the integer division operation. There are N stages of 1-bit division in an integer division operation, where N is the width of the quotient. Each stage generates a 1-bit quotient and partial-remainder. In the last stage, the final quotient and remainder are generated. 1-bit division uses an adder-subtractor to compare the partial remainder and denominator to get a new partial remainder. Quotient-digit selection is based on the sign of the partial remainder. In the last stage, the partial remainder is corrected to get the final remainder.

The Divider IP core supports configurable output latency. The latency can be any number of clock cycles from 1 to N. When latency is set to the value M, M stages of output registers are uniformly distributed into the N stages of 1-bit division operation. The final division stage always has output registers.

Implements Integer Division - The Divider IP core implements integer division with the formula: Numerator = Denominator * Quotient + Remainder

Uses a Non-Restoring Division Algorithm - The Divider IP core uses a non-restoring division algorithm to implement the integer division operation. There are N stages of 1-bit division in an integer division operation, where N is the width of the quotient. In the last stage, the final quotient and remainder are generated. 1-bit division uses an adder-subtractor to compare the partial remainder and denominator to get a new partial remainder. In the last stage, the partial remainder is corrected to get the final remainder.

Supports Configurable Output Latency - The Divider IP core supports configurable output latency. The latency can be any number of clock cycles from 1 to N. When latency is set to the value M, M stages of output registers are uniformly distributed into the N stages of 1-bit division operation. The final division stage always has output registers.

Features

  • Supports signed or unsigned numerator and denominator
  • Supports numerator and denominator data width 4-64
  • Supports forced positive remainder
  • Supports configurable output latency
  • Optional clock enable and data valid ports

The Divider IP core is available as an IPexpress user configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a bitstream may have countdown-timer logic included unless a license for the IP is purchased.

Jump to

Block Diagram

Resource Utilization

Avant Family
LAV-AT-500E-3LFG1156C
Configuration Clk Fmax (MHz)* Registers LUTs EBRs
Default 217 829 716 0
Numerator Data Width: 4,
Denominator Data Width: 4,
Output Latency: 1,
Others = Default
250 9 74 0
Numerator Data Width: 10,
Denominator Data Width: 20,
Output Latency: 10,
Others = Default
188 499 656 0
Numerator Data Type: SIGNED,
Denominator Data Type: SIGNED,
Others = Default
196 839 844 0
Numerator Data Width: 64,
Denominator Data Width: 64,
Output Latency: 64,
Others = Default
207 16381 16701 0

*Note: Fmax is generated when the FPGA design only contains Divider IP Core, and the target frequency is 200MHz. These values may be reduced when user logic is added to the FPGA design.

LAV-AT-500E-1LFG1156C
Configuration Clk Fmax (MHz)* Registers LUTs EBRs
Default 184 829 716 0
Numerator Data Width: 4,
Denominator Data Width: 4,
Output Latency: 1,
Others = Default
250 9 74 0
Numerator Data Width: 10,
Denominator Data Width: 20,
Output Latency: 10,
Others = Default
161 499 656 0
Numerator Data Type: SIGNED,
Denominator Data Type: SIGNED,
Others = Default
162 839 844 0
Numerator Data Width: 64,
Denominator Data Width: 64,
Output Latency: 64,
Others = Default
181 16381 16701 0

*Note: Fmax is generated when the FPGA design only contains Divider IP Core, and the target frequency is 200MHz. These values may be reduced when user logic is added to the FPGA design.

Nexus Family
LFMXO5-25-9BBG400I
Configuration Clk Fmax (MHz)* Registers LUTs EBRs
Default 200 829 341 0
Numerator Data Width: 4,
Denominator Data Width: 4,
Output Latency: 1,
Others = Default
200 9 40 0
Numerator Data Width: 10,
Denominator Data Width: 20,
Output Latency: 10,
Others = Default
200 499 301 0
Numerator Data Type: SIGNED,
Denominator Data Type: SIGNED,
Others = Default
187 821 472 0
Numerator Data Width: 64,
Denominator Data Width: 64,
Output Latency: 64,
Others = Default
154 12540 4609 0

*Note: Fmax is generated when the FPGA design only contains Divider IP Core, and the target Frequency is 200 MHz. These values may be reduced when user logic is added to the FPGA design

LFMXO5-25-7BBG400I
Configuration Clk Fmax (MHz)* Registers LUTs EBRs
Default 149 829 341 0
Numerator Data Width: 4,
Denominator Data Width: 4,
Output Latency: 1,
Others = Default
200 9 40 0
Numerator Data Width: 10,
Denominator Data Width: 20,
Output Latency: 10,
Others = Default
145 499 301 0
Numerator Data Type: SIGNED,
Denominator Data Type: SIGNED,
Others = Default
122 821 475 0
Numerator Data Width: 64,
Denominator Data Width: 64,
Output Latency: 64,
Others = Default
97 12540 4609 0

*Note: Fmax is generated when the FPGA design only contains Divider IP Core, and the target Frequency is 200 MHz. These values may be reduced when user logic is added to the FPGA design.

20-bit numerator
10-bit denominator
20 output latency
LatticeECP3 LatticeECP2/M LatticeXP2
Minimum Device Required LFE3-17EA LFE2-6E LFXP2-5E
Targeted Device LFE3-35EA-8FN672C LFE2-35E-7F672C LFXP2-30E-7F672C
Registers 828 828 886
LUTs 311 311 368
Slices 446 446 484
24-bit numerator
12-bit denominator
12 output latency
LatticeECP3 LatticeECP2/M LatticeXP2
Minimum Device Required LFE3-17EA LFE2-6E LFXP2-5E
Targeted Device LFE3-35EA-8FN672C LFE2-35E-7F672C LFXP2-30E-7F672C
Registers 586 586 619
LUTs 409 409 442
Slices 409 409 431
32-bit numerator
32-bit denominator
32 output latency
LatticeECP3 LatticeECP2/M LatticeXP2
Minimum Device Required LFE3-17EA LFE2-6E LFXP2-5E
Targeted Device LFE3-35EA-8FN672C LFE2-35E-7F672C LFXP2-30E-7F672C
Registers 3127 3123 3137
LUTs 1459 1459 1458
Slices 1791 1788 1791

1. Performance and utilization data are generated using Lattice Diamond 2.0 and Synopsys® Synplify™ Pro for Lattice F-2012.03L software. Performance may vary when using a different software version or targeting a different device density or speed grade within a given FPGA family.

Ordering Information

Device Family Part Numbers
Single Design Multi-Site Subscription
Avant-E DIVIDE-AVE-U DIVIDE-AVE-UT DIVIDE-AVE-US
MachXO5-NX DIVIDE-XO5-U DIVIDE-XO5-UT DIVIDE-XO5-US
CertusPro-NX DIVIDE-CPNX-U DIVIDE-CPNX-UT DIVIDE-CPNX-US
Certus-NX DIVIDE-CTNX-U DIVIDE-CTNX-UT DIVIDE-CTNX-US
CrossLink-NX DIVIDE-CNX-U DIVIDE-CNX-UT DIVIDE-CNX-US
LatticeECP3 DIVIDE-E3-U DIVIDE-E3-UT DIVIDE-E3-US
LatticeECP2M DIVIDE-PM-U DIVIDE-PM-UT -
LatticeECP2 DIVIDE-P2-U DIVIDE-P2-UT -
LatticeXP2 DIVIDE-X2-U DIVIDE-X2-UT -

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the Divider IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Divider IP Core - User Guide
FPGA-IPUG-02130 1.4 12/5/2023 PDF 614.9 KB
Parallel RapidIO User's Guide
11/1/2005 PDF 1.2 MB
Divider IP Core User's Guide
IPUG108 1.0 6/26/2012 PDF 1.3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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IP Module Evaluation Tutorial
8/1/2004 PDF 216.1 KB
IPexpress Quick Start Guide
8/5/2010 PDF 304.8 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Evaluation Package for Parallel RapidIO for LatticeECP/EC FPGA
1/1/2005 ZIP 1.6 MB

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