Divider IP Core

A One-Clock Divider that Supports Configurable Output Latency

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The Lattice Divider IP core is a one-clock divider which completes one integer division every clock. It supports signed or unsigned inputs and provides configurable output latency.

Latest Resource Utilization details are available in the IP Core User Guide.

Features

  • Supports signed or unsigned numerator and denominator
  • Supports numerator and denominator data width 4-64
  • Supports forced positive remainder
  • Supports configurable output latency
  • Optional clock enable and data valid ports

The Divider IP core is available as an IPexpress user configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a bitstream may have countdown-timer logic included unless a license for the IP is purchased.

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Block Diagram

Divider IP Core Block DiagramExpand Image

注文情報

ファミリ 部品番号
LatticeECP3 DIVIDE-E3-U
LatticeECP2 DIVIDE-P2-U
LatticeECP2M DIVIDE-PM-U
LatticeXP2 DIVIDE-X2-U

購入について：IPコアの購入方法はラティスの営業担当にお問い合わせください。

ドキュメント

Quick Reference
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
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Divider IP Core - User Guide
FPGA-IPUG-02130 1.7 12/11/2025 PDF 734.6 KB
Divider IP Core User's Guide
IPUG108 1.0 6/26/2012 PDF 1.3 MB
Parallel RapidIO User's Guide
11/1/2005 PDF 1.2 MB
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Divider IP Core - Release Notes
FPGA-RN-02090 1.1 12/12/2025 PDF 245.4 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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IP Module Evaluation Tutorial
8/1/2004 PDF 216.1 KB
IPexpress Quick Start Guide
8/5/2010 PDF 304.8 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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Evaluation Package for Parallel RapidIO for LatticeECP/EC FPGA
1/1/2005 ZIP 1.6 MB

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