OpenLDI/FPD-Link/LVDS Transmitter IP Core

Convert Video Streams from OpenLDI/FDP-Link/LVDS to Pixel Clock Domain

Related Products

Related Applications

The Lattice Semiconductor FPD-Link Transmitter IP translates parallel video streams to a Low Voltage Differential Signaling (LVDS) interface for a Flat Panel Display Link FPD-Link) connection to a display. The IP converts pixel data into the standard OpenLDI serial video interface domain.

Resource Utilization details are available in the IP Core User Guide.

Features

  • Compliant with Open LVDS Display Interface (OpenLDI) v0.95 specifications
  • Transmits in OpenLDI unbalanced operating mode format
  • Supports RGB888 and RGB666 video formats
  • Supports transmitting in Dual Channel Flat Panel Display Link Protocol (7:1 LVDS)
  • Supports 3-4 LVDS data lanes per channel

Block Diagram

FPD-LINK-TransmitterExpand Image

Resource Utilization

For Avant family
LAV-AT-500E-3LFG1156C
Configuration Clk Fmax (MHz) Slice Registers LUTs EBRs
Default 200 18 29 0
Number of TX Channels = 2, Others = Default 200 18 29 0
Data Type = RGB666, Others = Default 200 18 29 0
Number of TX Channels = 2, Data Type = RGB666, Others = Default 200 18 29 0

Note: Above shows the resource utilization of the OpenLDI/FPD-LINK/LVDS Transmitter Core for the LAV-AT-500E-3LFG1156C device using Lattice Synthesis Engine of the Lattice Radiant software. Default configuration is used and some attributes are changed from the default value to show the effect on the resource utilization.

For Nexus family (CrossLink-NX)
LIFCL-40-9BG400I
Configuration Clk Fmax (MHz) Slice Registers LUTs EBRs
Default 200 18 40 0
Number of TX Channels = 2, Others = Default 200 18 39 0
Data Type = RGB666, Others = Default 200 18 40 0
Number of TX Channels = 2, Data Type = RGB666, Others = Default 200 18 39 0

Notes: Above shows the resource utilization of the OpenLDI/FPD-LINK/LVDS Transmitter Core for the LIFCL-40-9BG400I device using Lattice Synthesis Engine of the Lattice Radiant software. Default configuration is used and some attributes are changed from the default value to show the effect on the resource utilization.

1. Fmax is generated when the FPGA design only contains OpenLDI/FPD-LINK/LVDS Transmitter Core and the target frequency is 135 MHz. These values may be reduced when user logic is added to the FPGA design.
2. The distributed RAM utilization is accounted for in the total LUT4s utilization. The actual LUT4 utilization is distribution among logic, distributed RAM, and ripple logic.

Ordering Information

IP core is available for FREE for use in Lattice Diamond design software. Please refer to the below Ordering Part Numbers for the Lattice Radiant design software.

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
Certus-N2 FPD-TX-CN2-UT FPD-TX-CN2-UX
Avant-G FPD-TX-AVG-UT FPD-TX-AVG-UX
Avant-X FPD-TX-AVX-UT FPD-TX-AVX-UX
Avant-E FPD-TX-AVE-UT FPD-TX-AVE-UX
MachXO5-NX FPD-TX-XO5-UT FPD-TX-XO5-UX
CertusPro-NX FPD-TX-CPNX-UT FPD-TX-CPNX-UX
Certus-NX FPD-TX-CTNX-UT FPD-TX-CTNX-UX
CrossLink-NX FPD-TX-CNX-UT FPD-TX-CNX-UX

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the FPD-Link Transmitter IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
OpenLDI/FPD-Link/LVDS Transmitter IP User Guide
FPGA-IPUG-02117 1.4 12/20/2024 PDF 2 MB
OpenLDI/FPD-LINK/LVDS Transmitter Interface IP Core - Lattice Diamond Software
FPGA-IPUG-02022 1.2 12/16/2020 PDF 2.1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
OpenLDI/FPD-Link/LVDS Transmitter IP Release Notes
FPGA-RN-02012 1.0 12/20/2024 PDF 217.6 KB

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