FPD-LINK Transmitter IP Core

Converts Pixel Data to LVDS Interface for an FPD-Link Connection to a Display

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The Lattice Semiconductor OpenLDI/FPD-LINK/LVDS Transmitter Interface IP translates parallel video streams to a Low Voltage Differential Signaling (LVDS) interface for a Flat Panel Display Link (FPD-Link) connection to a display. The increasing demand for better display technology makes bridging applications popular. FPD-Link is a common application interface. Similar to Channel Link and Camera Link, FPD-Link also uses LVDS interface for the physical layer.

Used in high-speed differential interface - The LVDS standard is commonly used in high-speed differential interface among consumer device, industrial control, medical, and automotive applications.

Advantage over single-ended technology - It offers low voltage, low power, and improved signal integrity which are advantages over single-ended technology.

Features

  • Compliant with Open LVDS Display Interface (OpenLDI) v0.95 specifications
  • Transmits in OpenLDI unbalanced operating mode format
  • Supports RGB888 and RGB666 video formats
  • Supports transmitting in Dual Channel Flat Panel Display Link Protocol (7:1 LVDS)
  • Supports 3-4 LVDS data lanes per channel

Block Diagram

FPD-LINK-Transmitter Block DiagramExpand Image

Resource Utilization

For Avant family
LAV-AT-500E-3LFG1156C
Configuration Clk Fmax (MHz) Slice Registers LUTs EBRs
Default 200 18 29 0
Number of TX Channels = 2, Others = Default 200 18 29 0
Data Type = RGB666, Others = Default 200 18 29 0
Number of TX Channels = 2, Data Type = RGB666, Others = Default 200 18 29 0

Note: Above shows the resource utilization of the OpenLDI/FPD-LINK/LVDS Transmitter Core for the LAV-AT-500E-3LFG1156C device using Lattice Synthesis Engine of the Lattice Radiant software. Default configuration is used and some attributes are changed from the default value to show the effect on the resource utilization.

For Nexus family (CrossLink-NX)
LIFCL-40-9BG400I
Configuration Clk Fmax (MHz) Slice Registers LUTs EBRs
Default 200 18 40 0
Number of TX Channels = 2, Others = Default 200 18 39 0
Data Type = RGB666, Others = Default 200 18 40 0
Number of TX Channels = 2, Data Type = RGB666, Others = Default 200 18 39 0

Notes: Above shows the resource utilization of the OpenLDI/FPD-LINK/LVDS Transmitter Core for the LIFCL-40-9BG400I device using Lattice Synthesis Engine of the Lattice Radiant software. Default configuration is used and some attributes are changed from the default value to show the effect on the resource utilization.

1. Fmax is generated when the FPGA design only contains OpenLDI/FPD-LINK/LVDS Transmitter Core and the target frequency is 135 MHz. These values may be reduced when user logic is added to the FPGA design.
2. The distributed RAM utilization is accounted for in the total LUT4s utilization. The actual LUT4 utilization is distribution among logic, distributed RAM, and ripple logic.

Ordering Information

  Part Number
Device Family Single Design Multi-Site Subscription
Avant-E FPD-TX-AVE-U FPD-TX-AVE-UT FPD-TX-AVE-US
MachXO5-NX FPD-TX-XO5-U FPD-TX-XO5-UT FPD-TX-XO5-US
CertusPro-NX FPD-TX-CPNX-U FPD-TX-CPNX-UT FPD-TX-CPNX-US
Certus-NX FPD-TX-CTNX-U FPD-TX-CTNX-UT FPD-TX-CTNX-US
CrossLink-NX FPD-TX-CNX-U FPD-TX-CNX-UT FPD-TX-CNX-US

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the FPD-Link Transmitter IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
OpenLDI/FPD-LINK/LVDS Transmitter Interface IP - Lattice Radiant Software
FPGA-IPUG-02117 1.1 4/8/2023 PDF 808.3 KB
OpenLDI/FPD-LINK/LVDS Transmitter Interface IP
FPGA-IPUG-02022 1.2 12/16/2020 PDF 2.1 MB

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