FPD-Link トランスミッタ

Note: Above shows the resource utilization of the OpenLDI/FPD-LINK/LVDS Transmitter Core for the LAV-AT-500E-3LFG1156C device using Lattice Synthesis Engine of the Lattice Radiant software. Default configuration is used and some attributes are changed from the default value to show the effect on the resource utilization.

Notes: Above shows the resource utilization of the OpenLDI/FPD-LINK/LVDS Transmitter Core for the LIFCL-40-9BG400I device using Lattice Synthesis Engine of the Lattice Radiant software. Default configuration is used and some attributes are changed from the default value to show the effect on the resource utilization.

1. Fmax is generated when the FPGA design only contains OpenLDI/FPD-LINK/LVDS Transmitter Core and the target frequency is 135 MHz. These values may be reduced when user logic is added to the FPGA design.
2. The distributed RAM utilization is accounted for in the total LUT4s utilization. The actual LUT4 utilization is distribution among logic, distributed RAM, and ripple logic.

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the FPD-Link Transmitter IP core, please contact your local Lattice Sales Office.