OpenLDI/FPD-Link/LVDS Receiver IP Core

Convert FPD-LINK Video Streams to Pixel Clock Domain

The Lattice Semiconductor FPD-Link Receiver IP translates video streams from a processor with an OpenLDI/FDP-Link/LVDS interface connection to the pixel clock domain. This IP can be used to connect with other application interfaces, such as the Mobile Industry Processor Interface (MIPIĀ®) Display Serial Interface (DSI), by integrating it with the Pixel-to-Byte Converter and CSI-2/DSI D-PHY Transmitter IP cores.

Resource Utilization details are available in the IP Core User Guide.

Features

  • Compliant with Open LVDS Display Interface (OpenLDI) v0.95 specifications.
  • Receives in OpenLDI unbalanced operating mode format.
  • Supports RGB888 and RGB666 video formats.
  • Supports receiving in Dual Channel Flat Panel Display Link protocol (7:1 LVDS).
  • Supports three to four LVDS data lanes per channel.

Block Diagram

Ordering Information

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
Avant-G FPD-RX-AVG-UT FPD-RX-AVG-US
Avant-X FPD-RX-AVX-UT FPD-RX-AVX-US
Avant-E FPD-RX-AVE-UT FPD-RX-AVE-US
CertusPro-NX FPD-RX-CPNX-UT FPD-RX-CPNX-US
MachXO5-NX FPD-RX-XO5-UT FPD-RX-XO5-US
CrossLink-NX FPD-RX-CNX-UT FPD-RX-CNX-US
Certus-NX FPD-RX-CTNX-UT FPD-RX-CTNX-US

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
OpenLDI/FPD-LINK/LVDS-Receiver Interface IP User Guide - Lattice Radiant Software
FPGA-IPUG-02116 1.2 6/28/2024 PDF 1 MB
OpenLDI/FPD-LINK/LVDS Receiver Interface IP User Guide - Lattice Diamond Software
FPGA-IPUG-02021 1.4 5/3/2024 PDF 1.8 MB

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