SubLVDS Image Sensor Receiver IP Core

Convert SubLVDS Image Sensor Video Stream to Pixel Clock Domain

The Lattice Semiconductor SubLVDS Image Sensor Receiver IP Core converts double data rate interface to pixel clock domain. The subLVDS interface is primarily used in image sensors. It has one clock pair and more than one data pairs. The number of data pairs varies, depending on bandwidth requirement.

Lower Common Mode Compared to LVDS Interface - Has lower common mode that is 0.9 V, while the common mode for LVDS is 1.25 V.

Lower Differential Swing Compared to LVDS Interface - Has lower differential swing that is ±150 mV, while the differential swing for LVDS is ±175 mV.

Source Synchronous Interface – Compared to LVDS Interface. the clock pair is running at the same rate as the data.

Features

  • Supports 4, 6, 8, 10, 12, 14, or 16 data lanes from an image sensor.
  • Supports 10-bit (RAW10) or 12-bit (RAW12) pixel widths.
  • Supports gearing of 8 and 16. The gearing 16 option is only for 4-lane configuration.
  • Supports APB Interface for register access and AXI4-Stream Transmit Interface.
  • Can generate XVS and XHS for image sensors operating in Passive mode.

Block Diagram

Resource Utilization

Number of RX Gears RX Gear Line Rate Synthesis Tool Register LUTs Fmax*
4 8 900 Mbps Synplify Pro 293 640 clk_p_i = 450 MHz
pixclk_o = 112.5 MHz
10 8 900 Mbps Synplify Pro 663 1214 clk_p_i = 450 MHz
pixclk_o = 112.5 MHz
16
8
900 Mbps Synplify Pro 874 1681 clk_p_i = 450 MHz
pixclk_o = 112.5 MHz
4 16 900 Mbps Synplify Pro 756 1622 clk_p_i = 450 MHz
pixclk_o = 56.25 MHz

*Note: The Fmax provided here is shown to give affirmation to the user that that target frequency for a certain bitrate is attainable. While it is possible that the maximum frequency could be higher than the one described below, the IP is bounded to limit it in order to maintain the user’s desired configuration.

Ordering Information

The SubLVDS Image Sensor Receiver IP core is available for FREE for use in Diamond design software.

For Radiant design software, the SubLVDS Image Sensor Receiver IP core must be purchased:

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
Avant-G LVDS-RX-AVG-UT LVDS-RX-AVG-US
Avant-X LVDS-RX-AVX-UT LVDS-RX-AVX-US
Avant-E LVDS-RX-AVE-UT LVDS-RX-AVE-US
MachXO5-NX LVDS-RX-XO5-UT LVDS-RX-XO5-US
CertusPro-NX LVDS-RX-CPNX-UT LVDS-RX-CPNX-US
CrossLink-NX LVDS-RX-CNX-UT LVDS-RX-CNX-US
Certus-NX LVDS-RX-CTNX-UT LVDS-RX-CTNX-US

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
SubLVDS Image Sensor Receiver IP Core
FPGA-IPUG-02093 1.8 12/5/2023 PDF 783.4 KB
SubLVDS Image Sensor Receiver Submodule IP - Lattice Diamond Software
FPGA-IPUG-02023 1.3 3/20/2020 PDF 1.8 MB

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