MIPI DSI/CSI-2 to Parallel Bridge Reference Design

Bridging Industrial Displays to Mobile Application Processors

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The Mobile Industry Processor Interface (MIPI®) D-PHY is developed primarily to support camera and display interconnections in mobile devices, and it has become the industry’s primary high-speed PHY solution for these applications in smartphones. It is typically used in conjunction with MIPI Camera Serial Interface-2 (CSI-2) and MIPI Display Serial Interface (DSI) protocol specifications. It meets the demanding requirements of low power, low noise generation, and high noise immunity that mobile phone designs demand.

MIPI D-PHY is a practical PHY for typical camera and display applications. It is designed to replace traditional parallel bus based on LVCMOS or LVDS. However, many processors and displays/cameras still use RGB, CMOS, or MIPI Display Pixel Interface (DPI) as interface.

The Lattice Semiconductor MIPI to Parallel with CertusPro™-NX, CrossLink™-NX and CrossLink reference design allows quick interface between a processor with a MIPI DSI and a display using RGB; or between a camera with a MIPI CSI-2 and a processor with a Parallel interface. The reference design provides this conversion for Lattice Semiconductor CertusPro-NX, CrossLink™-NX and CrossLink devices. This is useful for wearables, tablets, human machine interfacing, medical equipment, and many other applications.

Support one clock lane and configurable number of data lanes – The MIPI D-PHY receive interface has one clock lane and configurable number of data lanes. The clock lane is center aligned to the data lanes. The MIPI D-PHY clock can either be continuous (high speed only) or non-continuous.

Support two primary clocks for the main video data path: byte clock and pixel clock – A GPLL is used to generate the pixel clock. The same GPLL can also be used to generate the continuous byte clock when the RX D-PHY is in non-continuous clock mode. The input to the GPLL is byte clock in continuous clock mode or ref clock in non-continuous clock mode.

Features

  • Supports 1, 2, or 4 data lanes and one clock lane
  • Continuous and non-continuous MIPI D-PHY clock
  • Supports dedicated End of Transmission short packet (EoTp)
  • MIPI DSI Video Mode operation of Non-Burst Mode with Sync Pulses and Non-Burst Mode with Sync Events
  • Compliance:
    • CertusPro-NX and CrossLink-NX - MIPI D-PHY v1.2, MIPI DSI v1.2, and MIPI CSI-2 v1.2 specifications
    • CrossLink - MIPI D-PHY v1.1, MIPI DSI v1.1, and MIPI CSI-2 v1.1 specifications

Jump to

Block Diagram

MIPI DSI/CSI-2 to Parallel Bridge Block Diagram for CertusPro-NX and CrossLink-NX

MIPI DSI/CSI-2 to Parallel Bridge Block Diagram for CrossLink

Resource Utilization

Configurations Targeting CertusPro-NX
Configuration LUT
(Utilization/Total)
FF
(Utilization/Total)
EBR
(Utilization/Total)
I/O
(Utilization/Total)
4-lane, Gear 8, Soft D-PHY, CSI-2, RAW14, 1 Pixels/clock 1637/79872 1113/80769 0/208 30/299
2-lane, Gear 8, Soft D-PHY, CSI-2, RAW8, 2 Pixels/clock 879/79872 651/80769 1/208 28/299
4-lane, Gear 8, Soft D-PHY, DSI, RGB888, 2 Pixels/clock 1781/79872 1083/80769 2/208 65/299
1-lane, Gear 8, Soft D-PHY, DSI, RGB666, 1 Pixels/clock 990/79872 662/80769 3/208 30/299
Configurations Targeting CrossLink-NX
Configuration LUT FF EBR I/O
4-lane, Gear 16, Hard D-PHY, DSI, RGB888, 4 Pixels/clock 6 5 3 103
1-lane, Gear 8, Hard D-PHY, DSI, RGB888, 1 Pixels/clock 2 2 1 31
4-lane, Gear 8, Hard D-PHY, CSI-2, RAW10, 1 Pixels/clock 3 3 2 26
1-lane, Gear 8, Soft D-PHY, CSI-2, RAW8, 1 Pixels/clock 2 2 1 19
Configurations Targeting CrossLink
Configuration LUT FF EBR I/O
4-lane, Gear 8, Hard D-PHY, CSI-2, RAW10, 1 Pixels/clock 1610 969 3 19
1-lane, Gear 16, Hard D-PHY, DSI, RGB888, 1 Pixels/clock 912 658 2 34
2-lane, Gear 8, Soft D-PHY, DSI, RGB666, 1 Pixels/clock 1106 667 1 34
1-lane, Gear 8, Soft D-PHY, CSI-2, RAW8, 1 Pixels/clock 658 447 1 21

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
CertusPro-NX MIPI DSI/CSI-2 to Parallel Bridge Reference Design - Source Code
7/4/2023 ZIP 151 MB
CrossLink-NX MIPI DSI/CSI-2 to Parallel Bridge Reference Design - User Guide
FPGA-RD-02213 1.0 3/2/2021 PDF 1.5 MB
CrossLink-NX MIPI DSI/CSI-2 to Parallel Bridge Reference Design - Source Code
3/2/2021 ZIP 10.5 MB
CertusPro-NX MIPI DSI/CSI-2 to Parallel Bridge Reference Design - User Guide
FPGA-RD-02238 1.2 7/4/2023 PDF 1.1 MB
CrossLink MIPI DSI/CSI-2 to Parallel Bridge Reference Design - User Guide
FPGA-RD-02285 1.0 1/29/2024 PDF 1.5 MB
CrossLink MIPI DSI/CSI-2 to Parallel Bridge Reference Design - Source Code
1/29/2024 ZIP 3.6 MB

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