The Mobile Industry Processor Interface (MIPI®) D-PHY is developed primarily to support camera and display interconnections in mobile devices, and it has become the industry’s primary high-speed PHY solution for these applications in smartphones. It is typically used in conjunction with MIPI Camera Serial Interface-2 (CSI-2) and MIPI Display Serial Interface (DSI) protocol specifications. It meets the demanding requirements of low power, low noise generation, and high noise immunity that mobile phone designs demand.
MIPI D-PHY is a practical PHY for typical camera and display applications. It is designed to replace traditional parallel bus based on LVCMOS or LVDS. However, many processors and displays/cameras still use RGB, CMOS, or MIPI Display Pixel Interface (DPI) as interface.
The Lattice Semiconductor MIPI to Parallel with CertusPro™-NX, CrossLink™-NX and CrossLink reference design allows quick interface between a processor with a MIPI DSI and a display using RGB; or between a camera with a MIPI CSI-2 and a processor with a Parallel interface. The reference design provides this conversion for Lattice Semiconductor CertusPro-NX, CrossLink™-NX and CrossLink devices. This is useful for wearables, tablets, human machine interfacing, medical equipment, and many other applications.
Support one clock lane and configurable number of data lanes – The MIPI D-PHY receive interface has one clock lane and configurable number of data lanes. The clock lane is center aligned to the data lanes. The MIPI D-PHY clock can either be continuous (high speed only) or non-continuous.
Support two primary clocks for the main video data path: byte clock and pixel clock – A GPLL is used to generate the pixel clock. The same GPLL can also be used to generate the continuous byte clock when the RX D-PHY is in non-continuous clock mode. The input to the GPLL is byte clock in continuous clock mode or ref clock in non-continuous clock mode.