​​I3C Filter IP Core​

Invisible Relay Safeguarding Target Devices by Filtering Malicious Traffic

Related Products

​​The I3C Filter IP functions as an invisible relay from the point of view of the Controller and Target devices on the bus. The IP must be connected between the Controller and all Target devices at the SDA and SCL ports. This IP protects all Target devices from malicious traffic generated from the Controller port based on a list of allowable commands set by the host.

The I3C Filter IP supports the I3C protocol. The IP can also be configured as an I2C Filter. In the I2C Filter mode, the IP is a subset of the SMBus protocol.

Resource Utilization details are available in the IP Core User Guide.​

Features

  • Provides four interfaces, namely, AHB-Lite, I3C Bus Controller, I3C Bus Target, and Interrupt.
  • Connected between a single Controller and multiple Target devices.
  • Compatible with MIPI I3C Specification v1.1.1 (SDR mode only).
  • Supports legacy I2C backward compatibility.
  • Configurable filter selection to either I3C filter or I2C filter.

Block Diagram

​I3C Filter IP Core Block DiagramExpand Image

Ordering Information

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
MachXO5-NX I3C-FILT-XO5-UT I3C-FILT-XO5-US
Bundled MIPI-BNDL-UT MIPI-BNDL-US

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the I3C Filter IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
I3C Filter IP Core - User Guide​
FPGA-IPUG-02257 1.0 6/28/2024 PDF 1.3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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I3C Filter IP Core – Release Notes​
FPGA-RN-02004 1.0 6/28/2024 PDF 181.8 KB

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