MachXO5T-NX Development Board

Enhances Secure Control PLD Functionality with Multiple Boot and PCI Express

The MachXO5T-NX Development Board features the LFMXO5-100T device in a 400-ball caBGA package. This device offers a variety of features and programmability that enhances Secure Control PLD functionality with Multiple Boot and PCI Express. Its cryptographic engine supports user-mode security features. Along with the cryptographic engine, numerous system functions are included such as four PLLs and 3,744 kbits of embedded RAM plus hardened implementations of I2C and SPI, LFMXO5-100T FPGAs feature one hard PCIe link layer IP block which supports PCIe Gen1, Gen2 with 1 or 2 x1 configuration, with flexible, high performance I/O support numerous single-ended and differential standards including LPDDR4 controller and SLVS.


  • Two Gbe PHY RJ45 connectors, with SGMII PHY support
  • Supports LPDDR4 up to 1066Mbps, x16 bits
  • Supports PCIe Gen2 x1 Edge Connector
  • Versa Headers bridge with Lattice ASC Demo Board to support L-ASC10
  • General Purpose Input/Output (GPIO) interface with PMOD, Arduino and Raspberry Pi boards

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Board Photos

Bottom View

Side View

Ordering Information

  • Ordering Part Number: LFMXO5-100T-EVN
  • Click here to find an authorized Lattice distributor near you


Quick Reference
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MachXO5T-NX Development Board - User Guide
FPGA-EB-02058 1.0 4/18/2023 PDF 3.5 MB
MachXO5T-NX Development Board - Quick Start Guide
QS070 1.0 4/18/2023 PDF 543.3 KB

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