I2C Slave Controller Reference Design

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Reference Design LogoI2C, or Inter-Integrated Circuit, is a popular serial interface protocol that is widely used in many electronic systems. The I2C interface is a two-wire interface capable of half-duplex serial communication at moderate to high speeds of up to a few megabits per second. The I2C system incorporates an addressing system to identify the multiple I2C ‘slaves’ on the I2C bus. An I2C system can have single or multiple masters. The two bidirectional lines of the I2C system are SDA (Serial Data) and SCL (Serial Clock). An important electrical feature of the I2C lines are that they are both made up of open drain ports and are pulled high by resistors.

This reference design illustrates the implementation of an I2C slave using an iCE40™ ultra low density FPGA. The I2C slave implements functions as a port expander via an I2C bus.


  • 7/10-bit slave address support
  • Supports repeated start operations
  • Interrupt generation logic
  • Standard and High-speed modes of operation
  • Verilog RTL, test bench

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Block Diagram

I2C Slave Controller

Performance and Size

Device Family Utilization (LUTs) Language fMAX (MHz) I/O Pins Architectural
iCE40™ 456 Verilog 97 68 N/A

Performance and resource utilization characteristics are generated using iCE-40LP1K-CM121 with iCEcube2 design software.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.


Technical Resources
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I2C Slave Controller - Source Code
RD1140 1.1 2/12/2015 ZIP 338.6 KB

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