I2C Master Controller

Related Products

Reference Design LogoI2C or Inter-Integrated Circuit is a popular serial interface protocol that is widely used in many electronic systems. The I2C interface is a two-wire interface capable of half-duplex serial communication at moderate to high speeds of up to a few megabits per second. There are thousands of I2C peripherals on the market today, ranging from data converters to video processors. The I2C bus is a good choice for designs that need to communicate with low-speed peripherals due to its simplicity and low cost.

The I2C Master Controller reference design is implemented in Verilog. The Lattice iCECube2™ Place and Route tool integrated with the Synplify Pro synthesis tool is used for the implementation of the design. The design can be targeted to other iCE40™ FPGA family members.


  • 7-bit slave address support
  • Supports operation at 100 KHz (Standard Mode) and 400 KHz (Fast Mode)
  • Supports repeated start operations
  • Interrupt generation logic
  • Verilog RTL, test bench

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Block Diagram

I2C Master Controller

Performance and Size

Device Family Utilization (LUTs) Language fMAX (MHz) I/O Pins Architectural
iCE40™ 285 Verilog 87 65 N/A

Performance and resource utilization characteristics are generated using iCE-40LP1K-CM121 with iCEcube2 design software.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.


Technical Resources
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I2C Master Controller Source Code
RD1139 1.1 2/12/2015 ZIP 658 KB

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