Advanced CNN Accelerator IP

Optimized for Convolutional Neural Network

Related Applications

The Lattice Semiconductor Advanced CNN Accelerator IP Core is a calculation engine for Deep Neural Network with fixed point weight. It calculates full layers of Neural Network including convolution layer, pooling layer, batch normalization layer, and fully connected layer by executing a sequence of firmware code with weight value, which is generated by Lattice SensAI™ Neural Network Compiler. The engine is optimized for convolutional neural network, so it can be used for vision-based application such as classification or object detection and tracking. The IP Core does not require an extra processor; it can perform all required calculations by itself.

Higher Throughput – 64 bit data path engine for Avant, and 32bit data path engine for Avant and CPNX FPGAs.

Faster Run Time – Vector ALU for enhanced pixelwise operations, and accelerated pre/post ML image processing algorithms.

Improved Performance – Supports 1 to 4 convolution engines.

Features

  • Supports higher throughput 64-bit data path engine for Avant-AT-E and Avant-AT-X devices, and 32-bit data path engine for Avant-AT-E, Avant-AT-X, and CertusPro-NX devices
  • Supports convolution layer, max pooling layer, global average pooling layer, batch normalization layer, and full connect layer
  • Supports AXI4 for external memory interface
  • Supports Vector ALU (Arithmetic Logic Unit) for enhanced pixelwise operations, and accelerated pre/post ML image processing algorithms
  • Provides configurable bit width of activation (16/8-bit)

Jump to

Block Diagram

Ordering Information

  Part Number
Device Family Single Seat Perpetual Single Seat Annual
Avant-X CNNADV-ACCEL-AVX-UT CNNADV-ACCEL-AVX-US
Avant-E CNNADV-ACCEL-AVE-UT CNNADV-ACCEL-AVE-US
CertusPro-NX CNNADV-ACCEL-CPNX-US CNNADV-ACCEL-CPNX-US

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
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Advanced CNN Accelerator IP Core - User Guide
FPGA-IPUG-02224 2.3 12/18/2025 PDF 805.3 KB

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