Advanced CNN Accelerator IP

Optimized for Convolutional Neural Network

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Related Applications

The Lattice Semiconductor Advanced CNN Accelerator IP Core is a calculation engine for Deep Neural Network with fixed point weight. It calculates full layers of Neural Network including convolution layer, pooling layer, batch normalization layer, and fully connected layer by executing a sequence of firmware code with weight value, which is generated by Lattice SensAIā„¢ Neural Network Compiler. The engine is optimized for convolutional neural network, so it can be used for vision-based application such as classification or object detection and tracking. The IP Core does not require an extra processor; it can perform all required calculations by itself.

Features

  • Support for convolution layer, max pooling layer, global average pooling layer, batch normalization layer, and full connect layer
  • AXI4 for external memory interface
  • New vector ALU for enhanced pixelwise operations
  • Configurable bit width of activation (16/8-bit)
  • Configurable number of memory blocks for tradeoff between resource and performance

Jump to

Block Diagram

Advanced CNN Accelerator IP Core

Performance and Size

Configuration FPGA clk, aclk (MHz)2 Registers LUTs LRAMs EBRs Logical DSP
MULT9,
MULT18
REG18,
PREADD9
LRAM_NUM : 15
SPD_NUM : 8
SPD_SIZE : 4
CONV_NUM : 4
CONV_M4 : 1
EN_VE : 0
EN_CONV5 : 1
EN_CONV7 : 1
EN_ARGMAX_POOL : 1
EN_MAXPOOL_S1 : 1
AVANT_EMUL : 1
Avant-E-500 200, 100 73425 75261 (Avant has no LRAMs, so ML SPD is made of EBRs) 415 1092, 5 -
LRAM_NUM : 7
SPD_NUM : 8
SPD_SIZE : 4
CONV_NUM : 1
CONV_M4 : 0
EN_VE : 1
EN_CONV5 : 1
EN_CONV7 : 1
EN_ARGMAX_POOL : 1
EN_MAXPOOL_S1 : 1
AVANT_EMUL : 0
LFCPNX-100 96, 96 34877 46382 7 174 180, 12 180, 180

1. Performance may very when using a different software version or targetting a different device density or speed grade.
2. The clk and sclk numbers are from timing closuer in ML demo and refernce designs release with sensAI 6.0.

Ordering Information

  Device Family
Device Family Single Design Multi-Site Subscription
Avant-E CNNADV-ACCEL-AVE-U CNNADV-ACCEL-AVE-UT CNNADV-ACCEL-AVE-US
CertusPro-NX CNNADV-ACCEL-CPNX-U CNNADV-ACCEL-CPNX-UT CNNADV-ACCEL-CPNX-US

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Advanced CNN Accelerator IP Core - Lattice Radiant Software
FPGA-IPUG-02224 1.0 3/13/2023 PDF 1 MB

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