The Lattice SPI Target IP Core allows the host inside the FPGA to communicate with an external SPI Controller device. The data size of the SPI transaction can be configured to be 8, 16, 24, or 32 bits. This IP is designed to use an internal FIFO of configurable depth to minimize the host intervention during data transfer. SPI Target IP Core supports all SPI clocking modes –combinations of Clock Polarity (CPOL) and Clock Phase (CPHA) to match the settings of external devices.
Latest Resource Utilization details are available in the IP Core User Guide.