SPI Target IP Core

SPI Bus Interface

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The SPI Target IP Core allows the host inside the FPGA to communicate with an external SPI Controller device. The data size of the SPI transaction can be configured to be 8, 16, 24, or 32 bits. The Serial Peripheral Interface (SPI) is a high-speed synchronous, serial, full-duplex interface that allows a serial bit stream of configured length (8, 16, 24, and 32 bits) to be shifted into and out of the device at a programmed bit transfer rate. The Serial Peripheral Interface (SPI) is a high-speed synchronous, serial, full-duplex interface that allows a serial bit stream of configured length (8, 16, 24, and 32 bits) to be shifted into and out of the device at a programmed bit-transfer rate.

Minimize the Host Intervention - This IP is designed to use an internal FIFO of configurable depth to minimize the host intervention during data transfer.

Supports All SPI Clocking Modes - SPI Target IP Core supports all SPI clocking modes – combinations of Clock Polarity (CPOL) and Clock Phase (CPHA) to match the settings of external devices.

Bridge Between LMMI/AHB-Lite/APB and Standard External SPI Bus Interfaces - The SPI Target IP provides a bridge between LMMI/AHB-Lite/APB and standard external SPI bus interfaces.

Features

  • Four-wire SPI interface (SCLK, SS, MOSI, MISO)
  • Configurable SPI data width (8, 16, 24, or 32 bits wide)
  • Transmit FIFO and Receive FIFO with configurable depth
  • Sending of defined static value when Transmit FIFO is empty
  • Independent target configuration and daisy chain configuration

Jump to

Block Diagram

SPI Target IP Core Block DiagramExpand Image

Resource Utilization

Targeted Device Configuration Clk Fmax (MHz)* Registers LUTs EBRs
LAV-AT-500E-3LFG1156I Default 169.64 476
 588 2
Interface: APB,
Others = Default		 154.08 393 416 2
Interface: LMMI,
Others = Default		 251.76 352 436 2
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 178.25 476 588 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 191.02 588 691 2
LFMXO5-25-9BBG400I Default 179.57 476 601 2
Interface: APB,
Others = Default		 158.76 393 421 2
Interface: LMMI,
Others = Default		 186.08 352 436 2
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 162.02 476 602 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 143.72 588 743 2
LFMXO5-25-7BBG400I Default 125.24 476 601 2
Interface: APB,
Others = Default		 138.97 393 421 2
Interface: LMMI,
Others = Default		 170.74 352 436 2
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 150.04 476 602 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 131.49 588 743 2
LFD2NX-40-9BG256I Default 166.25 451 618 2
Interface: APB,
Others = Default		 137.97 368 439 2
Interface: LMMI,
Others = Default		 200 303 416 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 155.74 600 754 2
Implementation of FIFO: LUT,
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 184.98 515 712 0
LIFCL-40-9BG400I Default 165.32 451 618 2
Interface: APB,
Others = Default		 146.59 368 439 2
Interface: LMMI,
Others = Default		 200 303 416 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 173.55 600 754 2
Implementation of FIFO: LUT,
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 169.35 515 712 0

*Note: Fmax is generated when the FPGA design only contains SPI Target IP Core, and the target frequency is 50 MHz. These values may be reduced when user logic is added to the FPGA design.

Ordering Information

Available for free to use in Lattice Radiant design software.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
SPI Target IP Core - User Guide
FPGA-IPUG-02070 2.0 2/1/2024 PDF 1.2 MB

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