SPI从设备IP核

SPI总线接口

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串行外设接口（SPI）是一种高速同步、串行、全双工接口，它能够将已配置长度（8、16、24、32位）的串行位流以预设的传输速率传入或传出设备。

特性

  • 后端LMMI接口
  • 时钟极性和时钟相位模式 – 00、01、10、11
  • 可配置的串行时钟周期
  • 可配置的数据宽度
  • 可配置的读写数据FIFO（8、16、24或32位宽度）

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Block Diagram

SPI Target IP Core Block Diagram放大图片

Resource Utilization

Targeted Device Configuration Clk Fmax (MHz)* Registers LUTs EBRs
LAV-AT-500E-3LFG1156I Default 169.64 476
 588 2
Interface: APB,
Others = Default		 154.08 393 416 2
Interface: LMMI,
Others = Default		 251.76 352 436 2
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 178.25 476 588 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 191.02 588 691 2
LFMXO5-25-9BBG400I Default 179.57 476 601 2
Interface: APB,
Others = Default		 158.76 393 421 2
Interface: LMMI,
Others = Default		 186.08 352 436 2
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 162.02 476 602 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 143.72 588 743 2
LFMXO5-25-7BBG400I Default 125.24 476 601 2
Interface: APB,
Others = Default		 138.97 393 421 2
Interface: LMMI,
Others = Default		 170.74 352 436 2
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 150.04 476 602 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 131.49 588 743 2
LFD2NX-40-9BG256I Default 166.25 451 618 2
Interface: APB,
Others = Default		 137.97 368 439 2
Interface: LMMI,
Others = Default		 200 303 416 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 155.74 600 754 2
Implementation of FIFO: LUT,
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 184.98 515 712 0
LIFCL-40-9BG400I Default 165.32 451 618 2
Interface: APB,
Others = Default		 146.59 368 439 2
Interface: LMMI,
Others = Default		 200 303 416 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 173.55 600 754 2
Implementation of FIFO: LUT,
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 169.35 515 712 0

*Note: Fmax is generated when the FPGA design only contains SPI Target IP Core, and the target frequency is 50 MHz. These values may be reduced when user logic is added to the FPGA design.

Ordering Information

Available for free to use in Lattice Radiant design software.

文档

快速参考
标题 编号 版本 日期 格式 文件大小
选择全部
SPI Target IP Core - User Guide
FPGA-IPUG-02070 2.0 2/1/2024 PDF 1.2 MB

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