SPI Controller IP Core

Control for SPI Target Devices

Related Products

Related Applications


Newsletter Subscription

The Lattice SPI Controller IP Core allows the host inside the FPGA to communicate with multiple external SPI Target devices. The data size of the SPI transaction can be configured to 8, 16, 24, or 32 bits. This IP is designed to use an internal FIFO of configurable depth to minimize the host intervention during data transfer. The SPI Controller IP Core supports all SPI clocking modes — combinations of Clock Polarity (CPOL) and Clock Phase (CPHA) to match the settings of external devices.

Latest Resource Utilization details are available in the IP Core User Guide.

Features

  • Four-wire SPI interface (SCLK, SS, MOSI, MISO)
  • Configurable SPI data width (8, 16, 24, or 32 bits wide)
  • Transmit FIFO and Receive FIFO with configurable depth
  • Configurable number of SPI Chip Select lines (1 to 8)

Jump to

Block Diagram

SPI Controller IP Core Block DiagramExpand Image

Resource Utilization

Targeted Device Configuration Clk Fmax (MHz)* Registers LUTs EBRs
LAV-AT-500E-3LFG1156 Default 191.13 451 686 2
Interface: APB,
Others = Default		 135.48 368 443 2
Interface: LMMI,
Others = Default		 221.44 303 441 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 211.42 600 731 2
Implementation of FIFO: LUT,
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 199.28 515 708 0
LFMXO5-25-9BBG400I Default 176.84 451 618 2
Interface: APB,
Others = Default		 157.51 368 439 2
Interface: LMMI,
Others = Default		 200 303 416 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 151.04 600 754 2
Implementation of FIFO: LUT,
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 196.04 515 712 0
LFCPNX-100-9BBG484I Default 165.1 451 618 2
Interface: APB,
Others = Default		 186.88 368 439 2
Interface: LMMI,
Others = Default		 200 303 416 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 149.84 600 754 2
Implementation of FIFO: LUT,
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 184.5 515 712 0
LFD2NX-40-9BG256I Default 166.25 451 618 2
Interface: APB,
Others = Default		 137.97 368 439 2
Interface: LMMI,
Others = Default		 200 303 416 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 155.74 600 754 2
Implementation of FIFO: LUT,
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 184.98 515 712 0
LIFCL-40-9BG400I Default 165.32 451 618 2
Interface: APB,
Others = Default		 146.59 368 439 2
Interface: LMMI,
Others = Default		 200 303 416 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 173.55 600 754 2
Implementation of FIFO: LUT,
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 169.35 515 712 0

*Note: Fmax is generated when the FPGA design only contains SPI Controller IP Core, and the target frequency is 50 MHz. These values may be reduced when user logic is added to the FPGA design.

Ordering Information

Available for free to use in Lattice Radiant design software.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
SPI Controller IP User Guide
FPGA-IPUG-02069 2.2 12/20/2024 PDF 1.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
SPI Controller IP Release Notes
FPGA-RN-02015 1.0 12/20/2024 PDF 221.3 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

ABOUT LATTICE

SALES

SUPPORT

FOLLOW