SPI マスタ IP コア

SPI スレーブデバイスの制御

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シリアル・ペリフェラル・インタフェース (SPI) は高速同期式、シリアル、全二重のインタフェースです。設定された長さ (8、16、24、32ビット) のシリアルビットストリームをプログラムされたビット転送レートでデバイスに入出力させることができます。ラティス SPI マスタ IP コアは、ディスプレイドライバ、SPI EPROM、A/D コンバータなどの外部 SPI スレーブデバイスとの通信に使用されます。

機能

  • 4線 SPI インタフェース (SCLK、SS、MOSI、MISO) をサポート
  • SPI データ幅 (8、16、24、32ビット幅) を設定可能
  • サイズ変更が可能な送信用 FIFO と 受信用 FIFO
  • スレーブセレクト信号の極性を個別に設定可能
  • すべてのSPI クロックモードをサポート (クロック極性と位相の組み合わせ)
  • 選択可能なメモリ-マップ・スレーブインタフェース: AHB-Lite、APB、LMMI

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Block Diagram

SPI Controller IP Core Block DiagramExpand Image

Resource Utilization

Targeted Device Configuration Clk Fmax (MHz)* Registers LUTs EBRs
LAV-AT-500E-3LFG1156 Default 191.13 451 686 2
Interface: APB,
Others = Default		 135.48 368 443 2
Interface: LMMI,
Others = Default		 221.44 303 441 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 211.42 600 731 2
Implementation of FIFO: LUT,
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 199.28 515 708 0
LFMXO5-25-9BBG400I Default 176.84 451 618 2
Interface: APB,
Others = Default		 157.51 368 439 2
Interface: LMMI,
Others = Default		 200 303 416 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 151.04 600 754 2
Implementation of FIFO: LUT,
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 196.04 515 712 0
LFCPNX-100-9BBG484I Default 165.1 451 618 2
Interface: APB,
Others = Default		 186.88 368 439 2
Interface: LMMI,
Others = Default		 200 303 416 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 149.84 600 754 2
Implementation of FIFO: LUT,
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 184.5 515 712 0
LFD2NX-40-9BG256I Default 166.25 451 618 2
Interface: APB,
Others = Default		 137.97 368 439 2
Interface: LMMI,
Others = Default		 200 303 416 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 155.74 600 754 2
Implementation of FIFO: LUT,
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 184.98 515 712 0
LIFCL-40-9BG400I Default 165.32 451 618 2
Interface: APB,
Others = Default		 146.59 368 439 2
Interface: LMMI,
Others = Default		 200 303 416 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 173.55 600 754 2
Implementation of FIFO: LUT,
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 169.35 515 712 0

*Note: Fmax is generated when the FPGA design only contains SPI Controller IP Core, and the target frequency is 50 MHz. These values may be reduced when user logic is added to the FPGA design.

Ordering Information

Available for free to use in Lattice Radiant design software.

資料

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
SPI Controller IP User Guide
FPGA-IPUG-02069 2.2 12/20/2024 PDF 1.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
SPI Controller IP Release Notes
FPGA-RN-02015 1.0 12/20/2024 PDF 221.3 KB

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