SPI Controller IP Core

Control for SPI Target Devices

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The Lattice SPI Controller IP Core is normally used to communicate with external SPI target devices such as display drivers, SPI EPROMS, and analog-to-digital converters. The Serial Peripheral Interface (SPI) is a high-speed synchronous, serial, full-duplex interface that allows a serial bitstream of configured length (8, 16, 24, and 32 bits) to be shifted into and out of the device at a programmed bit-transfer rate.

Minimize the Host Intervention - This IP is designed to use an internal FIFO of configurable depth to minimize the host intervention during data transfer.

Supports All SPI Clocking Modes - SPI Controller IP Core supports all SPI clocking modes – combinations of Clock Polarity (CPOL) and Clock Phase (CPHA) to match the settings of external devices.

Bridge Between LMMI/AHB-Lite/APB and Standard External SPI Bus Interfaces - The SPI Controller IP provides a bridge between LMMI/AHB-Lite/APB and standard external SPI bus interfaces. On the external, off-chip side the SPI Controller IP has a standard SPI bus interface. On the internal, on-chip side, the SPI Controller IP has LMMI/AHB-Lite/APB interface depending on the Interface attribute settings.

Features

  • Supports four-wire SPI interface (SCLK, SS, MOSI, MISO)
  • Configurable SPI data width (8, 16, 24, or 32 bits wide)
  • Supports Transmit FIFO and Receive FIFO with configurable depth
  • Configurable number of SPI Chip Select lines (1 to 8).

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Block Diagram

SPI Controller IP Core Block DiagramExpand Image

Resource Utilization

Targeted Device Configuration Clk Fmax (MHz)* Registers LUTs EBRs
LAV-AT-500E-3LFG1156 Default 191.13 451 686 2
Interface: APB,
Others = Default		 135.48 368 443 2
Interface: LMMI,
Others = Default		 221.44 303 441 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 211.42 600 731 2
Implementation of FIFO: LUT,
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 199.28 515 708 0
LFMXO5-25-9BBG400I Default 176.84 451 618 2
Interface: APB,
Others = Default		 157.51 368 439 2
Interface: LMMI,
Others = Default		 200 303 416 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 151.04 600 754 2
Implementation of FIFO: LUT,
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 196.04 515 712 0
LFCPNX-100-9BBG484I Default 165.1 451 618 2
Interface: APB,
Others = Default		 186.88 368 439 2
Interface: LMMI,
Others = Default		 200 303 416 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 149.84 600 754 2
Implementation of FIFO: LUT,
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 184.5 515 712 0
LFD2NX-40-9BG256I Default 166.25 451 618 2
Interface: APB,
Others = Default		 137.97 368 439 2
Interface: LMMI,
Others = Default		 200 303 416 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 155.74 600 754 2
Implementation of FIFO: LUT,
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 184.98 515 712 0
LIFCL-40-9BG400I Default 165.32 451 618 2
Interface: APB,
Others = Default		 146.59 368 439 2
Interface: LMMI,
Others = Default		 200 303 416 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 173.55 600 754 2
Implementation of FIFO: LUT,
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 169.35 515 712 0

*Note: Fmax is generated when the FPGA design only contains SPI Controller IP Core, and the target frequency is 50 MHz. These values may be reduced when user logic is added to the FPGA design.

Ordering Information

Available for free to use in Lattice Radiant design software.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
SPI Controller IP Core - User Guide
FPGA-IPUG-02069 2.1 1/8/2024 PDF 1.1 MB

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