SPI主控IP核

SPI从设备控制

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串行外设接口（SPI）是一种高速同步、串行、全双工接口，它能够将已配置长度（8、16、24、32位）的串行位流以预设的传输速率传入或传出设备。莱迪思SPI主控IP核通常用于与外部SPI从设备通信，例如显示屏驱动、SPI EPROMS和模数转换器。

特性

  • 支持4线SPI接口（SCLK、SS、MOSI、MISO）
  • SPI数据宽度可配置（8、16、24或32位宽度）
  • 支持可配置深度的发送FIFO和接收FIFO
  • 每条从设备选择线极性可编程
  • 支持所有SPI时钟模式（时钟极性和时钟相位的组合）
  • 可选的内存映射从设备接口：AHB-Lite、APB或LMMI

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Block Diagram

SPI Controller IP Core Block Diagram放大图片

Resource Utilization

Targeted Device Configuration Clk Fmax (MHz)* Registers LUTs EBRs
LAV-AT-500E-3LFG1156 Default 191.13 451 686 2
Interface: APB,
Others = Default		 135.48 368 443 2
Interface: LMMI,
Others = Default		 221.44 303 441 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 211.42 600 731 2
Implementation of FIFO: LUT,
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 199.28 515 708 0
LFMXO5-25-9BBG400I Default 176.84 451 618 2
Interface: APB,
Others = Default		 157.51 368 439 2
Interface: LMMI,
Others = Default		 200 303 416 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 151.04 600 754 2
Implementation of FIFO: LUT,
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 196.04 515 712 0
LFCPNX-100-9BBG484I Default 165.1 451 618 2
Interface: APB,
Others = Default		 186.88 368 439 2
Interface: LMMI,
Others = Default		 200 303 416 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 149.84 600 754 2
Implementation of FIFO: LUT,
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 184.5 515 712 0
LFD2NX-40-9BG256I Default 166.25 451 618 2
Interface: APB,
Others = Default		 137.97 368 439 2
Interface: LMMI,
Others = Default		 200 303 416 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 155.74 600 754 2
Implementation of FIFO: LUT,
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 184.98 515 712 0
LIFCL-40-9BG400I Default 165.32 451 618 2
Interface: APB,
Others = Default		 146.59 368 439 2
Interface: LMMI,
Others = Default		 200 303 416 2
FIFO Depth: 256,
TX FIFO Almost Empty Flag: 255,
RX FIFO Almost Full Flag: 255,
Others = Default		 173.55 600 754 2
Implementation of FIFO: LUT,
TX FIFO Almost Empty Flag: 1,
RX FIFO Almost Full Flag: 1,
Others = Default		 169.35 515 712 0

*Note: Fmax is generated when the FPGA design only contains SPI Controller IP Core, and the target frequency is 50 MHz. These values may be reduced when user logic is added to the FPGA design.

Ordering Information

Available for free to use in Lattice Radiant design software.

文档

快速参考
标题 编号 版本 日期 格式 文件大小
选择全部
SPI Controller IP Core - User Guide
FPGA-IPUG-02069 2.1 1/8/2024 PDF 1.1 MB

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