AHB-Lite to APB Bridge Module

High-speed AHB-Lite and low power APB Interface

The Lattice Semiconductor AHB-Lite to APB Bridge Module provides an interface between the high-speed AHB-Lite and the low power APB. In many applications, the AHB-Lite system runs on a higher frequency clock with the APB system. This module has an optional clock crossing bridge, which can be enabled during IP configuration.

The design is implemented in Verilog HDL. The IP can be configured and generated using the Lattice Propel Builder software.


  • Compliance with AMBA 3 AHB-Lite Protocol v1.0 and AMBA 3 APB Protocol v1.0
  • Data Bus width of up to 32 bits [8, 16, 32]
  • Address width of up to 32-bits [11,12,...,32]
  • Support of optional clock domain crossing bridge
  • Registered output
Lattice Propel


Quick Reference
Select All
AHB-Lite to APB Bridge Module - Lattice Propel Builder
FPGA-IPUG-02053 1.3 12/5/2023 PDF 399.2 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.