Ethernet MAC Cores

The Ethernet Media Access Controller (MAC) core can be configured to operate in either the Gigabit mode (1000 Mbits/sec data rate) or the Fast Ethernet mode (10/100 Mbits/sec data rate). Netlist configurations of this core operate only in either the Gigabit mode or Fast Ethernet mode. The netlist cannot auto-negotiate between the two different modes.

The Ethernet MAC transmits and receives data between a host processor and an Ethernet network. The main function of the Ethernet MAC is to ensure that the Media Access rules specified in the 802.3 IEEE standard are met while transmitting a frame of data over Ethernet. Figure 2 shows the transmission of data on the Ethernet network using the frame format. On the receiving side, the Ethernet MAC extracts the different components of a frame and transfers them to higher applications through the FIFO interface.

Features

Compliant to IEEE 802.3z Standard
Generic Host Interface
Configurable 8-bit or 16-bit and Greater Data Bus
16-bit Wide Internal Data Path
Full-duplex Operation in Gigabit Mode
Full and Half Duplex in 10/100 Mode
Transmit and Receive Statistics Vector
Programmable Inter Packet Gap (IPG)
Multicast Address Filtering
Supports:
- Full-duplex Control Using PAUSE Frames
- VLAN Tagged Frames
- Automatic Re-transmission on Collision
- Automatic Padding of Short Frames
- Optional FCS Transmission and Reception
- Optional MII Management Interface Module
Supports Jumbo Frames up to 8192 kbytes
Reference Design for GMII to RGMII Bridge
- Reduced pincount Gigabit Media Independent Interface

Block Diagram

Performance and Size

Evaluation Configurations Available for Series 4 ORCA FPGAs and FPSCs¹
Name of Parameter File	Mode (Mbps)	CPU Data Width	MIIM Module	LUTs	ORCA 4 PFUs	Registers	External Pins	System EBRs (RAM512)	fMAX (MHz)
ether_fast_o4_3_002.lpc	10/100	16	Yes	2581	548	1850	198	2	62.5 MHz sys_clk, 25MHz MII host clks (PHY side)
ether_1gig_o4_3_001.lpc	1000	16	No	1747	364	1313	201	1	125MHz (GMII)

¹ Performance and utilization characteristics using ispLEVER^TM software and targeting the ORCA4E04-2BA352C. When using this IP Core in a different density, package, speed or grade within the ORCA 4 family, performance may vary.

Evaluation Configurations Available for ispXPGA¹
Name of Parameter File	Mode (Mbps)	CPU Data Width	MIIM Module	LUTs	PFUs	Registers	External Pins	System EBRs	fMAX
ether_1gig_xp_1_001.lpc	1000	16	No	2084	744	1502	201	4	125 MHz (GMII)
ether_fast_xp_1_002.lpc	10/100	16	Yes	3545	1156	2179	198	2	62.5 MHz sys_clk, 25MHz MII host clks (PHY side)

¹ Performance and utilization characteristics using ispLEVER^TM software and targeting the LFX500B-04FH516C device. The evaluation version of this IP core only works on this specific device density, package, and speed grade.

Evaluation Configurations Available for LatticeECP and LatticeEC¹
Name of Parameter File	Mode (Mbps)	CPU Data Width	MIIM Module	LUT4s	SLICEs	Registers	I/Os	System EBRs	fMAX
ether_1gig_e2_3_001.lpc	1000	16	No	1681	1318	1339	201	2	125 MHz (GMII)
ether_fast_e2_3_006.lpc	10/100	16	Yes	2712	1892	1792	198	4	62.5 MHz sys_clk, 25MHz MII host clks (PHY side)

¹ Performance and utilization characteristics are generated using LFEC20E-4F672C in Lattice ispLEVER v.4.1 software. When using this IP core in a different density, package, or speed grade, performance may vary.

Evaluation Configurations Available for LatticeXP¹
Name of Parameter File	Mode (Mbps)	CPU Data Width	MIIM Module	LUT4s	SLICEs	Registers	I/Os	System EBRs	fMAX
ether_1gig_xm_3_001.lpc	1000	16	No	1730	1328	1340	201	2	125 MHz (GMII)
ether_fast_xm_3_006.lpc	10/100	16	Yes	3008	1892	1839	198	4	62.5 MHz sys_clk, 25MHz MII host clks (PHY side)

¹ Performance and utilization characteristics are generated using LFXP10C-4F388C in Lattice ispLEVER 5.0 software. When using this IP core in a different density, package, or speed grade, performance may vary.

Evaluation Configurations Available for LatticeSC¹
Name of Parameter File	Mode (Mbps)	CPU Data Width	MIIM Module	LUT4s	SLICEs	Registers	I/Os	System EBRs	fMAX
ether_1gig_sc_3_001.lpc	1000	16	No	1929	1301	1333	201	1	125 MHz (GMII)
ether_fast_sc_3_006.lpc	10/100	16	Yes	2856	1910	1831	198	2	62.5 MHz sys_clk, 25MHz MII host clks (PHY side)

Ordering Information

Ordering Part Numbers:
- For ORCA 4 Fast Ethernet : ETHER-FAST-O4-N3
- For ORCA 4 Gigabit: ETHER-1GIG-O4-N3
- For ispXPGA Fast Ethernet: ETHER-FAST-XP-N3
- For ispXPGA Gigabit: ETHER-1GIG-XP-N3
- For LatticeECP/EC Fast Ethernet: ETHER-FAST-E2-N3
- For LatticeECP/EC Gigabit: ETHER-1GIG-E2-N3
- For LatticeXP Fast Ethernet: ETHER-FAST-XM-N3
- For LatticeXP Gigabit: ETHER-1GIG-XM-N3
- For LatticeSC Fast Ethernet: ETHER-FAST-SC-N3
- For LatticeSC Gigabit: ETHER-1GIG-SC-N3

To find out how to purchase the Ethernet MAC IP Cores, please contact your local Lattice Sales Office.

Documentation

Quick Reference

User Manual

Information Resources

Tutorials

Downloads

Downloadable IP

TITLE	NUMBER	VERSION	DATE	FORMAT	SIZE
Select All
Ethernet MAC User Guide	IPUG09		3/1/2006	PDF	501.6 KB

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TITLE	NUMBER	VERSION	DATE	FORMAT	SIZE
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IP Module Evaluation Tutorial			8/1/2004	PDF	216.1 KB

TITLE	NUMBER	VERSION	DATE	FORMAT	SIZE
Select All
Evaluation Package for Ethernet MAC 10/100 Mbps for ispXPGA			12/1/2003	ZIP	4.1 MB
Evaluation Package for Ethernet MAC 10/100 Mbps for LatticeECP/EC			9/1/2004	ZIP	957.4 KB
Evaluation Package for Ethernet MAC 10/100 Mbps for LatticeXP			5/1/2005	ZIP	1.5 MB
Evaluation Package for Ethernet MAC 10/100 Mbps for ORCA 4			10/1/2003	ZIP	918.7 KB
Evaluation Package for Gigabit Ethernet MAC for ispXPGA			12/1/2003	ZIP	3.4 MB
Evaluation Package for Gigabit Ethernet MAC for LatticeECP/EC			9/1/2004	ZIP	789.6 KB
Evaluation Package for Gigabit Ethernet MAC for LatticeXP			5/1/2005	ZIP	1.3 MB
Evaluation Package for Gigabit Ethernet MAC for ORCA 4			10/1/2003	ZIP	769.7 KB

Ethernet MAC Cores

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