莱迪思解决方案

演示

拥有故障记录功能的电源时序演示

使用L-ASC10监视和控制来自中心控制点的四个独立电源平面。带时间戳的故障记录。可扩展。

Platform Manager 2 & L-ASC10, MachXO3 

Mixed-Signal, Power Management, TOR Switch, Guidance Systems, 5G, Defense, SDR, Smart munitions 

IP Core

​​eSPI Target IP核​

莱迪思eSPI Target IP核符合英特尔eSPI规范，且在用户界面中拥有自己的虚拟线通道。

MachXO5-NX, Mach-NX, MachXO3D, MachXO3, MachXO2 , MachXO4 

APB, AHB-Lite, Lattice Sentry, OCP 

IP Core

RISC-V MC CPU IP核

Propel IP模块：具有可选的定时器和PIC子模块的32位RISC-V处理器核，通过AHB-Lite总线连接到其他Propel各类IP模块。

Certus-N2, MachXO3D, Certus-NX, CrossLink-NX, Avant-E, MachXO5-NX, CertusPro-NX, MachXO3, MachXO2 , Avant-G, Avant-X, MachXO4 

AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive, SDR, Avionics 

IP Core

RISC-V SM CPU IP核

RISC-V SM CPU IP可以在处理数据和指令时处理外部中断。该IP支持RV32I指令集、外部中断和调试，遵循JTAG – IEEE 1149.1标准。

Certus-N2, Avant-E, MachXO5-NX, Certus-NX, CertusPro-NX, CrossLink-NX, MachXO3D, MachXO3, MachXO2 , Avant-G, Avant-X, iCE40 Ultra/UltraLite 

AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive, SDR 

IP Core

RISC-V Nano CPU IP Core

The RISC-V Nano CPU IP contains a 32-bit RISC-V processor core that supports the RV32I instruction set and a lightweight interrupt merge controller.

Certus-N2, Avant-E, Avant-G, Avant-X, MachXO5-NX, CrossLink-NX, CertusPro-NX, Certus-NX, MachXO3D, MachXO2 , iCE40 UltraPlus, MachXO4 

Soft Processor, RISC-V, Lattice Propel, Lattice Diamond, Lattice Radiant, Defense, AHB-Lite 

IP Core

定时器/计数器IP

莱迪思半导体定时器/计数器IP用于跟踪系统中的超时，并在检测到超时时向CPU生成中断。

Certus-NX, CrossLink-NX, Avant-E, Avant-G, Avant-X, CertusPro-NX, CrossLink, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 LP/HX, iCE40 Ultra/UltraLite, iCE40 UltraPlus, LatticeECP2/M, LatticeECP3, LatticeSC/M, LatticeXP2, Mach-NX, MachXO, MachXO2 , MachXO3, MachXO3D, MachXO5-NX, Certus-N2 

AMBA, Lattice Propel, Lattice Diamond, Lattice Radiant, APB, AHB-Lite, Lattice Sentry, Lattice Sentry PFR IP Package, Security 

IP Core

​​M-PESTI Initiator IP核

莱迪思M-PESTI IP核可在系统启动前检测外设存在和属性采集。

Certus-N2, Avant-G, Avant-X, Avant-E, MachXO5-NX, MachXO3D, MachXO3, Mach-NX 

MPESTI, UART, APB, Lattice Sentry, OCP 

Reference Design

MPESTI Initiator Reference Design

MPESTI Initiator Reference Design provides the solution template which is compliant with the MPESTI Base Specification.

Avant-E, MachXO5-NX, MachXO3, MachXO3D 

MPESTI, UART, APB, AHB, RISC-V, OCP 

Reference Design

APB to AHB-Lite Bridge Reference Design

The APB to AHB-Lite Bridge Reference Design provides an interface between the low power APB and the high-speed AHB-Lite.

MachXO3D, MachXO3, MachXO2  

APB, AHB, AMBA 

IP Core

DC-SCM LVDS Tunneling Protocol and Interface (LTPI) IP Core

LTPI IP Core is an Open Computer Project Data Center – Secure Control Module Standards compatible solution which is introduced in the DC-SCM 2.0 Specification.

CertusPro-NX, CrossLink-NX, Certus-NX, MachXO3, MachXO3D, MachXO5-NX, Mach-NX, MachXO4 

CRC, LVDS, LTPI, AMBA, APB, Lattice Diamond, Lattice Radiant, Lattice Sentry, OCP 

Reference Design

JTAG Embedded Programming using RPi Reference Design

Demo connects Raspberry Pi GPIO pins to JTAG source code in Lattice Radiant™ and Diamond™ software for embedded development and hardware testing.

MachXO2 , MachXO3, MachXO3D, CertusPro-NX, CrossLink-NX, MachXO5-NX, Mach-NX, Certus-NX 

JTAG, Raspberry Pi, GPIO 

Reference Design

LVDS Tunneling Protocol and Interface Reference Design

The DC-SCM 2.0 LTPI Reference Design provides multiple solution compliant with DC-SCM 2.0 with a standardized DC-SCI and aggregating multiple data channels.

MachXO5-NX, MachXO3D, MachXO3, Mach-NX 

CRC, LVDS, I2C, GPIO, UART, LTPI, AMBA, APB, Lattice Diamond, Lattice Propel, OCP 

Reference Design

SSPI Embedded Programming using RPi Reference Design

SSPI Embedded Programming reference design provides several benefits, such as low power consumption and reasonable CPU, GPU, and memory performance.

CertusPro-NX, CrossLink-NX, CrossLinkPlus, CrossLink, MachXO3, MachXO2  

SSPI, Raspberry Pi 

Reference Design

I2C to APB Bridge Reference Design

With support APB read / write capability, the I2C to APB Bridge Reference Design converts external I2C Master into APB Master transaction.

MachXO2 , MachXO3, MachXO3D 

I2C, APB, AMBA, AHB 

IP Core

Helion IONOS图像信号处理IP系列

来自Helion Vision的全面、高质量、可自行配置的ISP解决方案，包括了从基本到高级的高动态范围成像（HDRI）色彩流水线。

MachXO, LatticeXP2, LatticeECP3, CrossLink, ECP5 / ECP5-5G, CrossLink-NX 

HDR, Image Processing, Video Tx/Rx, Lattice mVision, Automotive, Avionics 

IP Core

SPI Sub IP Core

The SPI Sub IP Core is a versatile, efficient solution for SPI communication between an FPGA and a microcontroller, SoC, or another FPGA.

Avant-E, Avant-G, Avant-X, MachXO5-NX, CertusPro-NX, Certus-NX, MachXO3, ECP5 / ECP5-5G 

AXI, SPI 

IP Core

USB 2.0 Device with FIFO Interface (USB20HF)

USB20HF IP Core provides FIFO & ULPI interface. It supports High Speed and Full Speed functionality for 15 IN/OUT endpoints.

CrossLink-NX, iCE40 UltraPlus, MachXO2  

FMC, Data Communication, Camera, ULPI, USB2, FIFO 

Reference Design

8N1 UART Transceiver Reference Design

8-bit data, no parity, and 1 stop bit Universal Asynchronous Receiver/Transmitter (UART) performs serial-to-parallel and parallel to serial conversions on data characters received from a peripheral device or CPU

iCE40 UltraPlus, MachXO2  

UART, Bus Controllers, TOR Switch 

IP Core

AHB-Lite互连模块

Propel IP模块：全参数化的软IP用于AHB-Lite系统——总线宽度8-1024位，地址宽度最大为32位，支持多达32个主控和32个从动设备。

Certus-N2, Avant-G, Avant-X, Avant-E, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO2 , MachXO3, MachXO3D, Mach-NX, MachXO5-NX, MachXO4 

AMBA, Lattice Propel, AHB-Lite, TOR Switch, Automotive 

IP Core

APB互连模块

Propel IP模块：完全参数化、最多可连接32个主控和32个从动设备。数据总线宽度最大为32位。地址宽度最大为32位。

Certus-N2, CertusPro-NX, Avant-E, Avant-G, Avant-X, MachXO2 , MachXO3, MachXO3D, Mach-NX, MachXO5-NX, CrossLink-NX, Certus-NX, iCE40 UltraPlus, MachXO4 

AMBA, APB, Lattice Propel, Automotive