莱迪思解决方案

IP Core

USB 2.0/3.2 IP核

莱迪思USB 2.0/3.2 IP核提供了一种连接USB主机的解决方案，适用于莱迪思CrossLink-NX FPGA最新器件。

CrossLink-NX 

USB, USB2, USB3, AHB, AHB-L, AHB-Lite, AXI, I2C, SPI, JTAG, LVDS, SLVS, FTDI 

Reference Design

USB到I/O聚合和桥接参考设计

USB到I/O桥接参考设计为支持USB的FPGA提供即插即用外设扩展，还支持从USB到I2C、SPI和GPIO的信号协议转换。

CrossLink-NX 

USB, USB2, USB3, I2C, SPI, JTAG, LVDS, SLVS, FTDI 

演示

USB到I/O聚合和桥接演示

USB到I/O聚合和桥接演示展示了莱迪思FPGA的功能，并加速了USB 2.0/3.2（5Gbps）接口创新。

CrossLink-NX 

USB, USB2, USB3, I2C, SPI, JTAG, LVDS, SLVS, FTDI 

演示

Crosslink-NX PCIe桥接板上的PCIe基础演示

该PCIe基础演示可以控制三个7段LED，并通过PCIe插槽操作FPGA的片上存储器。

CrossLink-NX, Certus-NX, CertusPro-NX 

SPI, Camera, CSI Camera, Ethernet, PCIe, PMOD, RJ-45, X/S/RGMII, UAVs, Automotive, Bus Controllers, Connectivity IP Suite, Defense, LED, Nexus PCIe 

演示

PCIe Colorbar Demo for Lattice Nexus-based FPGAs

PCIe Colorbar Demo displays a series of moving colorbars by streaming the image data using DMA transfers from the FPGA to the host system.

CrossLink-NX, Certus-NX, CertusPro-NX 

SPI, Camera, CSI Camera, Ethernet, PCIe, PMOD, RJ-45, X/S/RGMII, UAVs, Automotive, Bus Controllers, Connectivity IP Suite, Defense, LED, Nexus PCIe 

演示

PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

The PCI Express DMA Throughput Demo allows to initiate DMA read and write transactions, transferring data from the host to the FPGA and vice versa.

CrossLink-NX, Certus-NX, CertusPro-NX 

SPI, Camera, CSI Camera, Ethernet, PCIe, PMOD, RJ-45, X/S/RGMII, UAVs, Automotive, Bus Controllers, Connectivity IP Suite, Defense, LED, Nexus PCIe 

演示

PCIe Multifunction Demo for Lattice Nexus-based FPGAs

Demonstrates the multifunction capabilities of the Crosslink-NX FPGA that allows access to GPIO, MDIO and I2C registers.

CrossLink-NX, Certus-NX 

SPI, Camera, CSI Camera, Ethernet, PCIe, PMOD, RJ-45, X/S/RGMII, UAVs, Automotive, Bus Controllers, Connectivity IP Suite, Defense, I2C, LED, GPIO, Nexus PCIe 

演示

用户追踪和旁观者检测演示

该演示示例使用CNN模型，在低功耗通用FPGA上运行，可检测和追踪多个人脸

CrossLink-NX 

Machine Learning/AI, Lattice sensAI, Image Processing, Camera, FaceI dentification 

Reference Design

目标分类参考设计

基于在莱迪思CertusPro-NX低功耗FPGA上运行的Mobilenet神经网络模型实现目标分类参考设计

CertusPro-NX, Avant-E, CrossLink-NX 

Machine Learning/AI, Lattice sensAI, Object Detection, Object Identification, Space 

演示

目标分类演示

使用CNN模型在低功耗通用FPGA上运行的目标检测、分类和追踪多个目标的演示

CertusPro-NX, Avant-E 

Machine Learning/AI, Lattice sensAI, Object Detection, Object Identification, Space 

Reference Design

手势检测

使用红外图像传感器实现基于AI的低功耗手势检测系统

iCE40 UltraPlus 

Machine Learning/AI, Gesture Detection, Lattice sensAI 

IP Core

RISC-V MC CPU IP核

Propel IP模块：具有可选的定时器和PIC子模块的32位RISC-V处理器核，通过AHB-Lite总线连接到其他Propel各类IP模块。

MachXO3D, Certus-NX, CrossLink-NX, Avant-E, MachXO5-NX, CertusPro-NX, MachXO3, MachXO2  

AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive 

IP Core

RISC-V RX CPU IP Core

Lattice RISC-V RX IP processes data and instructions while monitoring the external interrupts, using 32-bit RISC-V processor core and several submodules.

Avant-E, MachXO5-NX, Certus-NX, CertusPro-NX, CrossLink-NX 

AHB-Lite, Soft Processor, RISC-V, RTOS, Lattice Propel, Defense, Automotive 

IP Core

RISC-V SM CPU IP核

RISC-V SM CPU IP可以在处理数据和指令时处理外部中断。该IP支持RV32I指令集、外部中断和调试，遵循JTAG – IEEE 1149.1标准。

Avant-E, MachXO5-NX, Certus-NX, CertusPro-NX, CrossLink-NX, MachXO3D, MachXO3, MachXO2  

AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive 

IP Core

Tightly-Coupled Memory (TCM) IP Core

The Tightly-Coupled Memory IP ensures low-latency automatic selection of the best memory type for user-selected application.

Avant-E, MachXO5-NX, Certus-NX, CertusPro-NX, CrossLink-NX 

Embedded Ram, FIFO, Lattice Propel, Lattice Diamond, Lattice Radiant 

IP Core

Lattice Sentry I2C Filter IP Core

Sentry I2C Filter IP Core provides an interface between I2C bus devices and a host processor while protecting against common I2C bus vulnerabilities.

Mach-NX, MachXO3D 

I2C, AHB-Lite, AHB-L, Lattice Propel, Lattice Sentry, Security, AMBA, FPGA, SMBus, RoT, Lattice Diamond, Lattice Sentry PFR IP Package 

IP Core

Lattice Sentry PLD Interface IP Core

Lattice Semiconductor Customer Programmable Logic Devices (PLD)implements a bidirectional mailbox for sending and receiving messages.

Mach-NX 

AHB-Lite, APB, FPGA, RTL, Lattice Propel, PLD, Lattice Sentry, Lattice Sentry PFR IP Package, Security 

IP Core

Lattice Sentry SMBus Mailbox IP Core

SMBus, a two-wire interface that support fairness arbitration and compatible with AHB-Lite specification. Target devices are Mach-NX and MachXO3D.

MachXO3D, Mach-NX 

I2C, AHB-L, Lattice Propel, Lattice Sentry, Security, SMBus, RoT, RTL, Lattice Sentry PFR IP Package 

IP Core

PIC IP Core

Lattice Semiconductor PIC soft IP with configurable 1~8 interrupt inputs and 32-bit AHB-L interface for Mach-NX FPGA

Mach-NX 

AHB-Lite, Lattice Propel, Lattice Diamond, Lattice Sentry, Lattice Sentry PFR IP Package, Security 

IP Core

SFB Interface IP Core

SFB allow access to AHB-L CPLD block , management CPU recovery circuit and Flash sector for read/write.

Mach-NX 

AHB-Lite, Lattice Propel, Lattice Sentry, Security, SPI, JTAG, Soc, CPLD, Lattice Sentry PFR IP Package