莱迪思解决方案

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  • FFT 编译器

    IP Core

    FFT 编译器

    The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT.
    FFT 编译器
  • FIR 滤波器生成器

    IP Core

    FIR 滤波器生成器

    可灵活配置的多通道FIR滤波器。最多支持256个通道,每个拥有2048个抽头。输入和系数宽度为4至32位。
    FIR 滤波器生成器
  • JESD204B IP核

    IP Core

    JESD204B IP核

    莱迪思JESD204B IP核是用于数据转换器和FPGA器件之间的高速串行接口,用于取代传统接口。
    JESD204B IP核
  • 10Gb Ethernet MAC+PHY IP Core

    IP Core

    10Gb Ethernet MAC+PHY IP Core

    The Lattice 10G Ethernet (GbE) IP core supports the ability to transmit and receive data between a host processor and an Ethernet network.
    10Gb Ethernet MAC+PHY IP Core
  • 25Gb以太网MAC+PHY IP核

    IP Core

    25Gb以太网MAC+PHY IP核

    莱迪思半导体的25G以太网(GbE)IP核支持在主机处理器和以太网网络之间发送和接收数据。
    25Gb以太网MAC+PHY IP核
  • PCI Express x1、x4 Root Complex Lite IP核

    IP Core

    PCI Express x1、x4 Root Complex Lite IP核

    Provides a PCI Express x1 and x4 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in PCIe protocol stack
    PCI Express x1、x4 Root Complex Lite IP核
  • Image Signal Processing IP Cores Suite

    IP Core

    Image Signal Processing IP Cores Suite

    The Lattice mVision ISP IP Core implements ISP pipelines for image quality enhancements in embedded designs based on Lattice FPGA devices.
    Image Signal Processing IP Cores Suite
  • MACsec AES256-GCM, High-speed (XIP1213H)

    IP Core

    MACsec AES256-GCM, High-speed (XIP1213H)

    The high-speed MACsec IP core implements the MACsec protocol as standardized in IEEE 802.1AE-2018, defining a security infrastructure for OSI model Layer 2 traffic.
    MACsec AES256-GCM, High-speed (XIP1213H)
  • QSPI闪存控制器IP核

    IP Core

    QSPI闪存控制器IP核

    QSPI闪存控制器IP可以通过标准、扩展的双/四、双或四通道SPI协议与多个外部SPI闪存器件进行通信。
  • Secure Connected Motion Control Platform

    Reference Design

    Secure Connected Motion Control Platform

    ​​This platform offers resilient connectivity, low power consumption, high performance, and robust security is increasing across various industries.​
    Secure Connected Motion Control Platform
  • USB 2.0/3.2 IP核

    IP Core

    USB 2.0/3.2 IP核

    莱迪思USB 2.0/3.2 IP核提供了一种连接USB主机的解决方案,适用于莱迪思CrossLink-NX FPGA最新器件。
    USB 2.0/3.2 IP核
  • USB到I/O聚合和桥接参考设计

    Reference Design

    USB到I/O聚合和桥接参考设计

    USB到I/O桥接参考设计为支持USB的FPGA提供即插即用外设扩展,还支持从USB到I2C、SPI和GPIO的信号协议转换。
    USB到I/O聚合和桥接参考设计
  • USB到I/O聚合和桥接演示

    演示

    USB到I/O聚合和桥接演示

    USB到I/O聚合和桥接演示展示了莱迪思FPGA的功能,并加速了USB 2.0/3.2(5Gbps)接口创新。
    USB到I/O聚合和桥接演示
  • 莱迪思和英伟达合作开发的网络边缘AI解决方案

    Reference Design

    莱迪思和英伟达合作开发的网络边缘AI解决方案

    该开发板充分集成到NVIDIA IGX/AGX™系统软件中,提供开源支持IP和易于编程的系统控制。
    莱迪思和英伟达合作开发的网络边缘AI解决方案
  • GHRD/GSRD Demonstration

    演示

    GHRD/GSRD Demonstration

    The Golden Hardware and Software Reference Design comprises of components for developing various kind of applications using CertusPro-NX Versa Board.
    GHRD/GSRD Demonstration
  • ML-KEM-512/768/1024 (CRYSTALS-Kyber), Balanced (XIP6110B)

    IP Core

    ML-KEM-512/768/1024 (CRYSTALS-Kyber), Balanced (XIP6110B)

    ML-KEM-512/768/1024 is an IP core for post-quantum Key Encapsulation Mechanism (KEM), optimized for a good balance between speed and resource requirements.
    ML-KEM-512/768/1024 (CRYSTALS-Kyber), Balanced (XIP6110B)
  • 用户追踪和旁观者检测演示

    演示

    用户追踪和旁观者检测演示

    该演示示例使用CNN模型,在低功耗通用FPGA上运行,可检测和追踪多个人脸
    用户追踪和旁观者检测演示
  • 目标分类参考设计

    Reference Design

    目标分类参考设计

    该参考设计展示了在网络边缘设备应用中实现基于机器学习的目标分类示例。
    目标分类参考设计
  • 目标分类演示

    演示

    目标分类演示

    该演示提供了在CertusPro-NX FPGA上运行的检测、分类和追踪多个目标的应用示例。
    目标分类演示
  • MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration

    演示

    MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration

    This demo illustrates L-ASC10 integration in a MachXO5-NX design and demonstrates RISC-V SOC interfacing with power sequencing and fault response.
    MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration
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