Lattice Solutions

Everything you need to quickly and easily complete your design

Share This Result >

Narrow Your Results



Solution Type



Device Support



























Tags






























































































































































































































































Providers

































Clear All
  • FFT Compiler IP Core

    IP Core

    FFT Compiler IP Core

    The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT.
    FFT Compiler IP Core
  • FIR Filter Generator IP Core

    IP Core

    FIR Filter Generator IP Core

    This IP core is a widely configurable, multi-channel FIR filter, implemented using high performance sysDSP™ blocks available in Lattice devices.
    FIR Filter Generator IP Core
  • ​​JESD204B IP Core​

    IP Core

    ​​JESD204B IP Core​

    ​​The Lattice JESD204B IP Core is a high-speed serial interface used between data converters, and the FPGA device to replace traditional interfaces.​
    ​​JESD204B IP Core​
  • 10Gb Ethernet MAC+PHY IP Core

    IP Core

    10Gb Ethernet MAC+PHY IP Core

    The Lattice 10G Ethernet (GbE) IP core supports the ability to transmit and receive data between a host processor and an Ethernet network.
    10Gb Ethernet MAC+PHY IP Core
  • 25Gb Ethernet MAC+PHY IP Core

    IP Core

    25Gb Ethernet MAC+PHY IP Core

    The Lattice Semiconductor 25G Ethernet (GbE) IP core supports the ability to transmit and receive data between a host processor and an Ethernet network.
    25Gb Ethernet MAC+PHY IP Core
  • PCI Express x1, x4 Root Complex Lite IP Core

    IP Core

    PCI Express x1, x4 Root Complex Lite IP Core

    Provides a PCI Express x1 and x4 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in PCIe protocol stack
    PCI Express x1, x4 Root Complex Lite IP Core
  • Image Signal Processing IP Cores Suite

    IP Core

    Image Signal Processing IP Cores Suite

    The Lattice mVision ISP IP Core implements ISP pipelines for image quality enhancements in embedded designs based on Lattice FPGA devices.
    Image Signal Processing IP Cores Suite
  • ​​I/O Aggregation Over USB with CrossLinkU-NX Reference Design​

    Reference Design

    ​​I/O Aggregation Over USB with CrossLinkU-NX Reference Design​

    USB to IO Bridging Reference Design Create plug-and-play peripheral expansion on USB-enabled FPGA & signal protocol conversion from USB to I2C, SPI, & GPIO.
    ​​I/O Aggregation Over USB with CrossLinkU-NX Reference Design​
  • Lattice and NVIDIA Edge AI Solution

    Reference Design

    Lattice and NVIDIA Edge AI Solution

    The board is fully integrated into NVIDIA IGX/AGX™ system software offering open-source enablement IP and easy programmable system control.
    Lattice and NVIDIA Edge AI Solution
  • MACsec AES256-GCM, High-speed (XIP1213H)

    IP Core

    MACsec AES256-GCM, High-speed (XIP1213H)

    The high-speed MACsec IP core implements the MACsec protocol as standardized in IEEE 802.1AE-2018, defining a security infrastructure for OSI model Layer 2 traffic.
    MACsec AES256-GCM, High-speed (XIP1213H)
  • QSPI Flash Controller IP Core

    IP Core

    QSPI Flash Controller IP Core

    The QSPI Flash Controller IP allows communication with multiple external SPI flash devices using standard, extended dual/quad, dual, or quad SPI protocols.
  • Secure Connected Motion Control Platform

    Reference Design

    Secure Connected Motion Control Platform

    ​​This platform offers resilient connectivity, low power consumption, high performance, and robust security is increasing across various industries.​
    Secure Connected Motion Control Platform
  • USB 2.0/3.2 IP Core

    IP Core

    USB 2.0/3.2 IP Core

    Lattice USB 2.0/3.2 IP Core provides a solution to interface with a USB host and can be targeted to the Lattice CrossLink-NX FPGA Devices.
    USB 2.0/3.2 IP Core
  • USB to I/O Aggregation and Bridging Demonstration

    Demo

    USB to I/O Aggregation and Bridging Demonstration

    The USB to I/O Aggregation and Bridging Demo shows the capabilities of the Lattice FPGA and accelerating USB 2.0/3.2 (5Gbps) Interface Innovation.
    USB to I/O Aggregation and Bridging Demonstration
  • GHRD/GSRD Demonstration

    Demo

    GHRD/GSRD Demonstration

    The Golden Hardware and Software Reference Design comprises of components for developing various kind of applications using CertusPro-NX Versa Board.
    GHRD/GSRD Demonstration
  • ML-KEM-512/768/1024 (CRYSTALS-Kyber), Balanced (XIP6110B)

    IP Core

    ML-KEM-512/768/1024 (CRYSTALS-Kyber), Balanced (XIP6110B)

    ML-KEM-512/768/1024 is an IP core for post-quantum Key Encapsulation Mechanism (KEM), optimized for a good balance between speed and resource requirements.
    ML-KEM-512/768/1024 (CRYSTALS-Kyber), Balanced (XIP6110B)
  • Object Classification Demonstration

    Demo

    Object Classification Demonstration

    This object classification demo provides a sample application for detecting, classifying, and tracking multiple objects running on CertusPro-NX FPGA.
    Object Classification Demonstration
  • Object Classification Reference Design

    Reference Design

    Object Classification Reference Design

    The Object Classification reference design shows examples on implementing machine-learning based object classification to edge devices applications.
    Object Classification Reference Design
  • User Tracking and Onlooker Detection Demonstration

    Demo

    User Tracking and Onlooker Detection Demonstration

    Sample demonstration for detection and tracking of multiple human faces running on a low power general purpose FPGA using CNN Model
    User Tracking and Onlooker Detection Demonstration
  • MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration

    Demo

    MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration

    This demo illustrates L-ASC10 integration in a MachXO5-NX design and demonstrates RISC-V SOC interfacing with power sequencing and fault response.
    MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration
  • Page 1 of 27
    First Previous
    1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
    Next Last