Lattice Solutions

Everything you need to quickly and easily complete your design

Solution Type


Device Support




















Tags



































































































Providers

















  • Key Phrase Detection

    Demo

    Key Phrase Detection

    Uses artificial intelligence (AI) to detect a specific key-phrase using a tiny, low-power iCE40 UltraPlus FPGA
    Key Phrase Detection
  • Key Phrase Detection

    Reference Design

    Key Phrase Detection

    Continuous searches for a key phrase utterance via a digital MEMS microphone. Can be re-configured to work with any trained word or phrase.
    Key Phrase Detection
  • Human Face Identification

    Reference Design

    Human Face Identification

    Uses a Convolutional Neural Network in the ECP5 FPGA to detect a human face, and match to known registered faces. Can be adapted to work with any other object.
    Human Face Identification
  • Human Presence Detection

    Reference Design

    Human Presence Detection

    Uses Lattice sensAI IP to continuously search for the presence of a human and reports results. Can be adapted to detect any other object.
    Human Presence Detection
  • Object Counting

    Reference Design

    Object Counting

    An example object counting application based on the Lattice sensAI stack. Includes SPI, DDR IP blocks, ISP engine, 8 CNN engines and a counting / overlay engine
    Object Counting
  • CNN Accelerator IP

    IP Core

    CNN Accelerator IP

    Implement AI solutions with CNNs from common or custom networks. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
    CNN Accelerator IP
  • CNN Compact Accelerator IP

    IP Core

    CNN Compact Accelerator IP

    Implement AI solutions with CNNs or BNNs that have power consumption in the mW range. Works with Lattice Neural Network Compiler software tool.
    CNN Compact Accelerator IP
  • CNN Plus Accelerator IP

    IP Core

    CNN Plus Accelerator IP

    Implement Ultra-Low Power AI solutions with CNNs. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
    CNN Plus Accelerator IP
  • Byte to Pixel Converter

    IP Core

    Byte to Pixel Converter

    Modular MIPI/D-PHY IP - Converts Parallel Data From a D-PHY Receiver into Pixel Format
    Byte to Pixel Converter
  • CSI-2/DSI D-PHY Receiver

    IP Core

    CSI-2/DSI D-PHY Receiver

    Modular MIPI/D-PHY IP - PHY for receiving MIPI CSI-2/DSI Data for further processing. Supports up to 4 MIPI lanes to 10Gb/s
    CSI-2/DSI D-PHY Receiver
  • CSI-2/DSI D-PHY Transmitter

    IP Core

    CSI-2/DSI D-PHY Transmitter

    Modular MIPI/D-PHY IP - PHY for transmitting MIPI CSI-2/DSI Data. Supports up to 4 MIPI lanes to 10Gb/s
    CSI-2/DSI D-PHY Transmitter
  • FPD-LINK Receiver

    IP Core

    FPD-LINK Receiver

    Modular MIPI/D-PHY IP - Converts FPD-LINK Video Streams to Pixel Clock Domain
    FPD-LINK Receiver
  • FPD-LINK Transmitter

    IP Core

    FPD-LINK Transmitter

    Modular MIPI/D-PHY IP - Convert Pixel Data Streams to an FPD-LINK Video Stream
    FPD-LINK Transmitter
  • Pixel to Byte Converter

    IP Core

    Pixel to Byte Converter

    Modular MIPI/D-PHY IP - Converts Pixel Format Data to Parallel Byte Format
    Pixel to Byte Converter
  • SubLVDS Image Sensor Receiver

    IP Core

    SubLVDS Image Sensor Receiver

    Modular MIPI/D-PHY IP - Converts SubLVDS Image Sensor Video Stream to Pixel Clock Domain
    SubLVDS Image Sensor Receiver
  • 1 to N MIPI CSI-2/DSI Duplicator

    Reference Design

    1 to N MIPI CSI-2/DSI Duplicator

    Modular MIPI/D-PHY Reference Design - Duplicate one MIPI CSI-2 channel to N DSI channels
    1 to N MIPI CSI-2/DSI Duplicator
  • 4 to 1 Image Aggregation with CrossLink-NX

    Reference Design

    4 to 1 Image Aggregation with CrossLink-NX

    Modular MIPI/D-PHY Reference Design - Aggregates four MIPI CSI-2 inputs to a single output stream.
    4 to 1 Image Aggregation with CrossLink-NX
  • MIPI CSI-2 Virtual Channel Aggregation

    Reference Design

    MIPI CSI-2 Virtual Channel Aggregation

    Modular MIPI/D-PHY Reference Design - Adaptable and flexible solution combines multiple MIPI CSI-2 inputs to a single CSI-2 output stream.
    MIPI CSI-2 Virtual Channel Aggregation
  • MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge

    Reference Design

    MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge

    Modular MIPI/D-PHY Reference Design - Complete solution integrates the Byte to Pixel Converter, CSI-2/DSI D-PHY Receiver and FPD-LINK (OpenLDI) Transmitter
    MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge
  • N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation

    Reference Design

    N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation

    Modular MIPI/D-PHY Reference Design - Aggregate multiple MIPI CSI-2 inputs up to 5 channels horizontally line by line to a single CSI-2 output
    N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation
  • Page 1 of 18
    First Previous
    1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
    Next Last
    Like most websites, we use cookies and similar technologies to enhance your user experience. We also allow third parties to place cookies on our website. By continuing to use this website you consent to the use of cookies as described in our Cookie Policy.