Lattice Solutions

Everything you need to quickly and easily complete your design

Share This Result >

Narrow Your Results



Solution Type



Device Support



























Tags






























































































































































































































































Providers

































Clear All
  • ​​I/O Aggregation Over USB with CrossLinkU-NX Reference Design​

    Reference Design

    ​​I/O Aggregation Over USB with CrossLinkU-NX Reference Design​

    USB to IO Bridging Reference Design Create plug-and-play peripheral expansion on USB-enabled FPGA & signal protocol conversion from USB to I2C, SPI, & GPIO.
    ​​I/O Aggregation Over USB with CrossLinkU-NX Reference Design​
  • 10Gb Ethernet MAC+PHY IP Core

    IP Core

    10Gb Ethernet MAC+PHY IP Core

    The Lattice 10G Ethernet (GbE) IP core supports the ability to transmit and receive data between a host processor and an Ethernet network.
    10Gb Ethernet MAC+PHY IP Core
  • 25Gb Ethernet MAC+PHY IP Core

    IP Core

    25Gb Ethernet MAC+PHY IP Core

    The Lattice Semiconductor 25G Ethernet (GbE) IP core supports the ability to transmit and receive data between a host processor and an Ethernet network.
    25Gb Ethernet MAC+PHY IP Core
  • Lattice and NVIDIA Edge AI Solution

    Reference Design

    Lattice and NVIDIA Edge AI Solution

    The board is fully integrated into NVIDIA IGX/AGX™ system software offering open-source enablement IP and easy programmable system control.
    Lattice and NVIDIA Edge AI Solution
  • PCI Express for Avant FPGAs

    IP Core

    PCI Express for Avant FPGAs

    The Lattice PCIe X8 IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express for Avant FPGAs
  • QSPI Flash Controller IP Core

    IP Core

    QSPI Flash Controller IP Core

    The QSPI Flash Controller IP allows communication with multiple external SPI flash devices using standard, extended dual/quad, dual, or quad SPI protocols.
  • Secure Connected Motion Control Platform

    Reference Design

    Secure Connected Motion Control Platform

    ​​This platform offers resilient connectivity, low power consumption, high performance, and robust security is increasing across various industries.​
    Secure Connected Motion Control Platform
  • USB 2.0/3.2 IP Core

    IP Core

    USB 2.0/3.2 IP Core

    Lattice USB 2.0/3.2 IP Core provides a solution to interface with a USB host and can be targeted to the Lattice CrossLink-NX FPGA Devices.
    USB 2.0/3.2 IP Core
  • USB to I/O Aggregation and Bridging Demonstration

    Demo

    USB to I/O Aggregation and Bridging Demonstration

    The USB to I/O Aggregation and Bridging Demo shows the capabilities of the Lattice FPGA and accelerating USB 2.0/3.2 (5Gbps) Interface Innovation.
    USB to I/O Aggregation and Bridging Demonstration
  • Object Classification Demonstration

    Demo

    Object Classification Demonstration

    This object classification demo provides a sample application for detecting, classifying, and tracking multiple objects running on CertusPro-NX FPGA.
    Object Classification Demonstration
  • Object Classification Reference Design

    Reference Design

    Object Classification Reference Design

    The Object Classification reference design shows examples on implementing machine-learning based object classification to edge devices applications.
    Object Classification Reference Design
  • PCIe Basic Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe Basic Demo for Lattice Nexus-based FPGAs

    The PCIe Basic Demo allows you to control three 7 segment LEDs and manipulate the onboard memory of the FPGA through the PCIe slot.
    PCIe Basic Demo for Lattice Nexus-based FPGAs
  • PCIe Colorbar Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe Colorbar Demo for Lattice Nexus-based FPGAs

    PCIe Colorbar Demo displays a series of moving colorbars by streaming the image data using DMA transfers from the FPGA to the host system.
    PCIe Colorbar Demo for Lattice Nexus-based FPGAs
  • PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

    The PCI Express DMA Throughput Demo allows to initiate DMA read and write transactions, transferring data from the host to the FPGA and vice versa.
    PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs
  • PCIe Multifunction Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe Multifunction Demo for Lattice Nexus-based FPGAs

    Demonstrates the multifunction capabilities of the Crosslink-NX FPGA that allows access to GPIO, MDIO and I2C registers.
    PCIe Multifunction Demo for Lattice Nexus-based FPGAs
  • User Tracking and Onlooker Detection Demonstration

    Demo

    User Tracking and Onlooker Detection Demonstration

    Sample demonstration for detection and tracking of multiple human faces running on a low power general purpose FPGA using CNN Model
    User Tracking and Onlooker Detection Demonstration
  • Hand Gesture Detection

    Reference Design

    Hand Gesture Detection

    Implements a low power AI based system to detect hand gestures using an IR image sensor
    Hand Gesture Detection
  • RISC-V MC CPU IP Core

    IP Core

    RISC-V MC CPU IP Core

    The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).
    RISC-V MC CPU IP Core
  • RISC-V RX CPU IP Core

    IP Core

    RISC-V RX CPU IP Core

    Lattice RISC-V RX IP processes data and instructions while monitoring the external interrupts, using 32-bit RISC-V processor core and several submodules.
    RISC-V RX CPU IP Core
  • RISC-V SM CPU IP Core

    IP Core

    RISC-V SM CPU IP Core

    Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
    RISC-V SM CPU IP Core
  • Page 1 of 27
    First Previous
    1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
    Next Last