SWAP-C FPGAs for Aerospace and Defense

Meet mission requirements with low power and high reliability Lattice FPGAs

Accelerate design cycles, reduce system costs and future proof designs with programmable solutions for a multitude of application from airborne platforms, communication systems, ISR and space missions. With over 40 years of heritage in delivering low power, programmable solutions, Lattice Semiconductor has a rich history of delivering SWAP-C optimized FPGAs for connectivity, signal processing, sensor fusion and machine learning solutions developed from ground-up to address the industry needs.

  • Industry leading low power FPGAs to meet thermal constraints and rugged application requirements
  • Innovative silicon and software solutions to meet domain specific safety, security and reliability requirements
  • World’s largest volume FPGA vendor with a robust supply chain built for assurance and longevity

Key Lattice FPGA Features & Benefits

  • Low power FPGAs that scale up to 637k System Logic Cells and up to 28 instances of 25Gbps Serdes optimized for edge connectivity and signal processing
  • Industry leading advanced security features including AES256-GCM, ECDSA 256-521 & RSA 2048-4096 with post quantum resilience, anti-tamper and hardened PUF to secure bitstream and protect user data during run-time
  • Low soft error rate, latch-up immunity (80 (MeVcm2)/mg @ T=125°C) with industry leading fast, hardened scrubber (SEDC) and fast secure boot independent of configuration bit technology
  • Design tools offer latest advancements in scripting, design partioning, timing analysis, high speed interface debug and third party tools integration for synthesis including TMR, simulation and verification

Defense

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Example Applications

Sensor Bridge Reference Design

  • Scalable, Low latency, open source sensor to compute platform
  • Diverse sensor connections from MIPI to RFs
  • RTL-based data plane and control plane packetizer
  • Easy programming and system control

机器人视觉和控制

  • 多通道摄像头/传感器桥接和聚合
  • 多通道摄像头/传感器预处理和同步
  • 实时同步、感知和控制,多轴
  • 内部软核CPU和/或外部CPU

数据包处理和电路板控制

  • 通过PCIe将CPU桥接到多个控制平面外设(I2C、UART、GPIO)、板卡管理功能以及高达25GE的控制平面流量
  • FPGA中实现的安全功能(例如加密、身份验证)有助于保护控制平面流量
  • 25G SerDes,支持PCIe Gen 4 x4(硬核IP)和25 Gb以太网
  • 快速FPGA配置支持电路板管理需求和PCIe启动时间要求

控制平面安全和硬件管理

  • 通过PCIe将CPU桥接到多个控制平面外设(I2C、UART、GPIO)、电路板管理功能和10GE控制平面通信
  • 在FPGA上实现安全功能(例如加密、身份验证)有助于保护控制平面通信
  • 10G SERDES支持 PCIe Gen 3 x 4(硬核 IP)和10 Gb以太网(硬核IP实现10GBASE-R PCS)
  • 由于采用FD-SOI技术,软错误率(SER)降低100倍,可实现极高的系统稳定性和长时间正常运行
  • FPGA快速配置支持电路板管理需求和PCIe启动时间要求

Secure Synchronization with Compliant 1588 PTP

High precision 1588 PTP time, frequency and phase synchronization, Supports secure authentication, message integrity and replay attack protection, Instant-on performance with better than Class C timing accuracy ,Complete customizable hardware and software solution to enable distributed architecture.

Guidance Systems

  • Programmable system integration with 5Gbps transceivers, embedded memory, DSP and MCU
  • Sensor fusion, any-to-any connectivity and embedded vision

Chain of Trust Implementation

  • Hardware Root-of-Trust is the first link in chain that protects mission critical compute and communication platforms
  • Hardened device configuration engine cryptographically authenticates MachXO3D’s configuration image at power-on
  • Embedded security block provides cryptographic functions to authenticate other platform firmware at power-on

Mixed Reality Head-Mount Display

  • Small form factor packaging to meet stringent signal processing requirements
  • Flexible interfaces to sensors, analog and RF front-ends

FPGAs Best Suited for Defense

  • Avant-X
    Avant-X FPGAs delivers the industry’s lowest power mid-range FPGA in small packages, enabling a cost effective solution for applications that require sensor processing, high-speed connectivity and proven reliability. With 28 Multi-protocol transceivers, class leading anti-tamper and latch-up immunity in harsh environments, Avant-X is well suited for advanced, integrated Aerospace & Defense solutions.
  • CertusPro-NX
    CertusPro-NX is optimized for bandwidth to compute density to help maximize system performance in small form factor. Leveraging the low power architecture and up to 8 ports of 10Gbps serdes coupled with a flexible wide range and high speed I/O for LPDDR4 simplify system design while keeping the FPGA power under 1W. Based on Nexus platform, the FPGA has been extensively tested for reliable operation in harsh environements.
  • Certus-NX
    Certus-NX is Built on Lattice Nexus platform with Up to 4x lower power vs. similar FPGAs and Up to 100x higher reliability based on 28 nm FD-SOI technology solves the most challenging problems in leading edge defense platforms.
  • CrossLink-NX
    The Crosslink-NX with low soft error rate and lowest power in its class enables efficient processing, bridging and management capabilities to solve challenging problems in Software Defined Radios, Guidance Systems and Unmanned Aerial Vehicle (UAV).
  • MachXO3D
    The MachXO3D is the root of trust enabler with all required features onboard on a monolithic silicon with small footprint and low power that could be deployed in systems of all sizes, offering the most compact solution for untrusted supply chain.

Leaded Package Overview

Lattice offers leaded packaging services to eliminate the risk for tin-whisker and to improve reliability in presence of high shock and vibration applications.

Lattice Packages Wirebond Flip Chip
Wafer Pad or Bump Lead free Lead free
Substrate bump or pad finish Lead free Lead free
Caps No Caps No Caps
Substrate Solder Balls Leaded Leaded
Package Reflow Leaded Leaded

Known Good Die Product Overview

Lattice offers a wide variety of known good die products, tested to full data sheet specification within the specified temperature range with full traceability for each die shipped.

Family Logic Density Test Method Programmability Temperature Range
LatticeECP3 150K Known Good Die Volatile -40 C to 125 C
LatticeXP2 40K Good Die Non-volatile -40 C to 125 C
ECP5 85K Known Good Die Volatile -40 C to 125 C
MachXO3 10K Known Good Die Non-volatile -40 C to 105 C

Reference Designs

GHRD/GSRD参考设计

Reference Design

GHRD/GSRD参考设计

黄金硬件和软件参考设计(GSRD)包括了使用基于CertusPro-NX Versa开发板开发各种应用所需的组件。
Lattice Sentry 4.0 SCM和HPM CPLD参考设计

Reference Design

Lattice Sentry 4.0 SCM和HPM CPLD参考设计

这是一个Sentry 4.0服务器解决方案平台的安全控制模块(SCM)和主机平台模块(HPM)的CPLD设计模板。
Lattice Sentry 4.0 SCM和HPM CPLD参考设计
场景分割参考设计

Reference Design

场景分割参考设计

使用莱迪思CrossLink-NX FPGA实现场景分割的高效、低功耗方法
场景分割参考设计
冗余电源管理

Reference Design

冗余电源管理

Uses a Lattice Power Manager II device to achieve Redundant Power Supply Management using the power supply OR’ing technique
冗余电源管理
莱迪思Sentry采用MachXO3D的可信根参考设计

Reference Design

莱迪思Sentry采用MachXO3D的可信根参考设计

该设计采用莱迪思Sentry IP帮助您开发和测试一套完整的符合NIST 800-193规范的PFR解决方案。您还可以对其进行修改满足特定需求。
莱迪思Sentry采用MachXO3D的可信根参考设计

IP Cores

Image Signal Processing IP Cores Suite

IP Core

Image Signal Processing IP Cores Suite

The Lattice mVision ISP IP Core implements ISP pipelines for image quality enhancements in embedded designs based on Lattice FPGA devices.
Image Signal Processing IP Cores Suite
PCI Express for Nexus FPGAs

IP Core

PCI Express for Nexus FPGAs

The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
PCI Express for Nexus FPGAs
RISC-V MC CPU IP核

IP Core

RISC-V MC CPU IP核

Propel IP模块:具有可选的定时器和PIC子模块的32位RISC-V处理器核,通过AHB-Lite总线连接到其他Propel各类IP模块。
RISC-V MC CPU IP核
RISC-V SM CPU IP核

IP Core

RISC-V SM CPU IP核

RISC-V SM CPU IP可以在处理数据和指令时处理外部中断。该IP支持RV32I指令集、外部中断和调试,遵循JTAG – IEEE 1149.1标准。
RISC-V SM CPU IP核
PCI Express for Avant FPGAs

IP Core

PCI Express for Avant FPGAs

The Lattice PCIe X8 IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
PCI Express for Avant FPGAs

Development Kits & Boards

Space Development Board by Adiuvo

Board

Space Development Board by Adiuvo

Developed by a team of experienced engineers for space and with prototyping space applications in mind, the board provides access to the commercial equivalent of the space grade Certus™-NX-RT, making it ideal for prototyping and test campaigns to increase the Technology Readiness Level.
Space Development Board by Adiuvo
LimeSDR Mini Development Board by Lime Microsystems

Board

LimeSDR Mini Development Board by Lime Microsystems

LimeSDR Mini Dev Board is a low cost, open source and apps-enabled SDR platform that can be used to support any type of wireless communication standard.
LimeSDR Mini Development Board by Lime Microsystems
搭载莱迪思MachXO5-NX器件的Sentry 4.0演示板

Board

搭载莱迪思MachXO5-NX器件的Sentry 4.0演示板

该完整的平台可帮助您开发和测试符合NIST 800-193标准的PFR解决方案,并帮助您使用Lattice Radiant和Propel 2024.1工具进行SoC项目开发。
搭载莱迪思MachXO5-NX器件的Sentry 4.0演示板
基于Mach-NX的莱迪思Sentry演示板

Board

基于Mach-NX的莱迪思Sentry演示板

这一完善的平台能够帮助您开发和测试符合NIST 800-193规范的PFR方案,包括实现调试、接口和拓展的各种特性。
基于Mach-NX的莱迪思Sentry演示板
CrossLink-NX评估板

Board

CrossLink-NX评估板

CrossLink-NX评估板载有一片40K逻辑单元的CrossLink-NX FPGA;可轻松访问FPGA上的大多数I/O和PCIe 5G SERDES; 拥有FPGA中间层板卡(FMC)、Raspberry Pi、MIPI CSI-2、D-PHY和通用接头,大大扩展了易用性。
CrossLink-NX评估板

Demos

GHRD/GSRD Demonstration

演示

GHRD/GSRD Demonstration

The Golden Hardware and Software Reference Design comprises of components for developing various kind of applications using CertusPro-NX Versa Board.
GHRD/GSRD Demonstration
MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration

演示

MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration

This demo illustrates L-ASC10 integration in a MachXO5-NX design and demonstrates RISC-V SOC interfacing with power sequencing and fault response.
MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration
莱迪思图像信号处理演示

演示

莱迪思图像信号处理演示

为嵌入式视觉开发套件提供基于ECP5 FPGA的完整ISP示例设计,非常适合工业、医疗和汽车应用。
莱迪思图像信号处理演示
拥有故障记录功能的电源时序演示

演示

拥有故障记录功能的电源时序演示

使用L-ASC10监视和控制来自中心控制点的四个独立电源平面。带时间戳的故障记录。可扩展。
拥有故障记录功能的电源时序演示
Crosslink-NX PCIe桥接板上的PCIe基础演示

演示

Crosslink-NX PCIe桥接板上的PCIe基础演示

该PCIe基础演示可以控制三个7段LED,并通过PCIe插槽操作FPGA的片上存储器。
Crosslink-NX PCIe桥接板上的PCIe基础演示

Quality Programs

Lattice is committed to Industry Leadership in the supply of high quality programmable logic components and software design tools.

Commitment to Defense

Lattice is committed to providing the Defense market with industry’s most complete portfolio optimized for SWAP-C, longest product life cycle and dedicated local engineering support.

Documentation

快速参考
资讯资源
标题 编号 版本 日期 格式 文件大小
选择全部
Implementing JOTP-051-Compliant Safety Features in Lattice FPGAs
FPGA-TN-02150 1.1 3/15/2021 PDF 855.2 KB
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-02076 2.1 7/18/2024 PDF 614.6 KB
Single Event Upset (SEU) Report for Nexus Platform
FPGA-TN-02174 1.6 8/1/2024 PDF 368 KB
标题 编号 版本 日期 格式 文件大小
选择全部
Implementing JOTP-051-Compliant Safety Features in Lattice FPGAs
FPGA-TN-02150 1.1 3/15/2021 PDF 855.2 KB
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-02076 2.1 7/18/2024 PDF 614.6 KB
Single Event Upset (SEU) Report for Nexus Platform
FPGA-TN-02174 1.6 8/1/2024 PDF 368 KB
标题 编号 版本 日期 格式 文件大小
选择全部
Defense Solutions Brief
I0271 Rev 1 8/4/2020 PDF 1.6 MB
标题 编号 版本 日期 格式 文件大小
选择全部
A Guide to the Benefits of the Lattice Nexus FPGA Platform for Mission-Critical Applications
WP0028 1.0 1/22/2021 PDF 449.4 KB

Support

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