莱迪思解决方案

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  • ​​eSPI Target IP核​

    IP Core

    ​​eSPI Target IP核​

    莱迪思eSPI Target IP核符合英特尔eSPI规范,且在用户界面中拥有自己的虚拟线通道。
    ​​eSPI Target IP核​
  • PIC IP Core

    IP Core

    PIC IP Core

    Lattice Semiconductor PIC soft IP with configurable 1~8 interrupt inputs and 32-bit AHB-L interface for Mach-NX FPGA
    PIC IP Core
  • SFB Interface IP Core

    IP Core

    SFB Interface IP Core

    SFB allow access to AHB-L CPLD block , management CPU recovery circuit and Flash sector for read/write.
    SFB Interface IP Core
  • 莱迪思Sentry PLD接口IP核

    IP Core

    莱迪思Sentry PLD接口IP核

    莱迪思半导体客户可编程逻辑器件(PLD)实现了发送和接收消息的双向邮箱功能。
    莱迪思Sentry PLD接口IP核
  • Lattice Sentry I2C Filter IP Core

    IP Core

    Lattice Sentry I2C Filter IP Core

    Sentry I2C Filter IP Core provides an interface between I2C bus devices and a host processor while protecting against common I2C bus vulnerabilities.
    Lattice Sentry I2C Filter IP Core
  • 莱迪思Sentry QSPI监视器IP核用于MachXO3D

    IP Core

    莱迪思Sentry QSPI监视器IP核用于MachXO3D

    用于莱迪思Sentry的Propel IP模块:监视SPI/QSPI总线上的通信,可识别和阻止潜在的非法通信。
    莱迪思Sentry QSPI监视器IP核用于MachXO3D
  • ​​M-PESTI Initiator IP核

    IP Core

    ​​M-PESTI Initiator IP核

    莱迪思M-PESTI IP核可在系统启动前检测外设存在和属性采集。
    ​​M-PESTI Initiator IP核
  • DC-SCM LVDS Tunneling Protocol and Interface (LTPI) IP Core

    IP Core

    DC-SCM LVDS Tunneling Protocol and Interface (LTPI) IP Core

    LTPI IP Core is an Open Computer Project Data Center – Secure Control Module Standards compatible solution which is introduced in the DC-SCM 2.0 Specification.
    DC-SCM LVDS Tunneling Protocol and Interface (LTPI) IP Core
  • JTAG Embedded Programming using RPi Reference Design

    Reference Design

    JTAG Embedded Programming using RPi Reference Design

    Demo connects Raspberry Pi GPIO pins to JTAG source code in Lattice Radiant™ and Diamond™ software for embedded development and hardware testing.
  • LVDS Tunneling Protocol and Interface Reference Design

    Reference Design

    LVDS Tunneling Protocol and Interface Reference Design

    The DC-SCM 2.0 LTPI Reference Design provides multiple solution compliant with DC-SCM 2.0 with a standardized DC-SCI and aggregating multiple data channels.
    LVDS Tunneling Protocol and Interface Reference Design
  • 莱迪思Sentry PFR平台可信根(PRoT)参考设计

    Reference Design

    莱迪思Sentry PFR平台可信根(PRoT)参考设计

    莱迪思Sentry PFR平台可信根设计支持Mach-NX和MachXO5-NX器件,具有低密度FPGA和增强的用户模式安全功能。
    莱迪思Sentry PFR平台可信根(PRoT)参考设计
  • Tektagon™ XFR Platform Root of Trust Hardware Security Solution

    IP Core

    Tektagon™ XFR Platform Root of Trust Hardware Security Solution

    Tektagon XFR - an integrated Platform Root of Trust solution using Lattice Sentry, with low-power secure control FPGAs running pre-verified, PFR-compliant IP.
    Tektagon™ XFR Platform Root of Trust Hardware Security Solution
  • AHB-Lite互连模块

    IP Core

    AHB-Lite互连模块

    Propel IP模块:全参数化的软IP用于AHB-Lite系统——总线宽度8-1024位,地址宽度最大为32位,支持多达32个主控和32个从动设备。
    AHB-Lite互连模块
  • AHB-Lite到APB桥接模块

    IP Core

    AHB-Lite到APB桥接模块

    Propel IP模块:将高速AHB-lite桥接到低功耗APB。数据总线宽度最大为32位。地址宽度最大为32位。
    AHB-Lite到APB桥接模块
  • APB互连模块

    IP Core

    APB互连模块

    Propel IP模块:完全参数化、最多可连接32个主控和32个从动设备。数据总线宽度最大为32位。地址宽度最大为32位。
    APB互连模块
  • I2C总线主控软核

    Reference Design

    I2C总线主控软核

    使用Verilog实现软核I2C总线主控,支持多款莱迪思FPGA系列
    I2C总线主控软核
  • UART IP核

    IP Core

    UART IP核

    Propel IP模块:类似于NS16450 UART的串行通信,支持RS-232。
    UART IP核
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