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  • SSPI Embedded Programming using RPi Reference Design

    Reference Design

    SSPI Embedded Programming using RPi Reference Design

    SSPI Embedded Programming reference design provides several benefits, such as low power consumption and reasonable CPU, GPU, and memory performance.
    SSPI Embedded Programming using RPi Reference Design
  • Helion IONOS Image Signal Processing IP Portfolio

    IP Core

    Helion IONOS Image Signal Processing IP Portfolio

    Comprehensive, high-quality, highly-configurable ISP solution from Helion Vision, from basic to advanced High Dynamic Range Imaging (HDRI) color pipelines.
    Helion IONOS Image Signal Processing IP Portfolio
  • OpenLDI/FPD-Link/LVDS Transmitter IP Core

    IP Core

    OpenLDI/FPD-Link/LVDS Transmitter IP Core

    The FPD-LINK Transmitter Interface IP translates DSI video streams to LVDS interface for an FDP-Link connection to displays.
    OpenLDI/FPD-Link/LVDS Transmitter IP Core
  • SubLVDS Image Sensor Receiver IP Core

    IP Core

    SubLVDS Image Sensor Receiver IP Core

    The subLVDS interface is primarily used in image sensors, integrating one clock pair and one or more data pairs.
    SubLVDS Image Sensor Receiver IP Core
  • MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge Reference Design

    Reference Design

  • MIPI DSI/CSI-2 to Parallel Bridge Reference Design

    Reference Design

    MIPI DSI/CSI-2 to Parallel Bridge Reference Design

    MIPI to Parallel allows quick interface between a processor and a display using RGB; or between a camera and a processor with a Parallel interface.
    MIPI DSI/CSI-2 to Parallel Bridge Reference Design
  • Parallel to MIPI CSI-2 / DSI Display Interface Bridge Reference Design

    Reference Design

    Parallel to MIPI CSI-2 / DSI Display Interface Bridge Reference Design

    Lattice Parallel to MIPI CSI-2/DSI Display Interface Bridge Reference Design supports low-power (LP) mode during vertical and horizontal blanking.
    Parallel to MIPI CSI-2 / DSI Display Interface Bridge Reference Design
  • SubLVDS to MIPI CSI-2 Image Sensor Bridge

    Reference Design

    SubLVDS to MIPI CSI-2 Image Sensor Bridge

    Modular MIPI/D-PHY Reference Design - Complete solution integrates the Pixel to Byte Converter, SubLVDS Image Sensor Recevier and CSI-2/DSI D-PHY Transmitter
    SubLVDS to MIPI CSI-2 Image Sensor Bridge
  • Soft I2C Bus Master

    Reference Design

    Soft I2C Bus Master

    Implements a soft I2C Bus Master in Verilog, supporting many Lattice FPGA families
    Soft I2C Bus Master
  • Soft I2C Slave Peripheral

    Reference Design

    Soft I2C Slave Peripheral

    Implements a soft I2C Slave Peripheral in Verilog, supporting many Lattice FPGA families
    Soft I2C Slave Peripheral
  • DPC CCM – Color correction

    IP Core

    DPC CCM – Color correction

    DPC CCM is designed to reduce the difference between the spectral characteristics of an image sensor and the spectral response of the human eye.
    DPC CCM – Color correction
  • DPC Color Conversion

    IP Core

    DPC Color Conversion

    DPC Color Conversion allows real-time conversion of the RGB colour space into the YCbCr colour space.
    DPC Color Conversion
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