FPD-LINK Receiver

Convert FPD-LINK Video Streams to Pixel Clock Domain

Due to the higher demand for better displays, bridging applications has become increasingly popular. One very common application interface is the Flat Panel Display Link (FPD-LINK) interface. The Low Voltage Differential Signaling (LVDS) standard is commonly used for high-speed differential interface in consumer devices, industrial control, medical and automotive. The LVDS interface offers low voltage, low power and improved signal integrity advantages over single-ended technology. Applications such as Channel Link, FPD-Link, and Camera Link use LVDS interface for physical layer.

7:1 LVDS interface is a popular standard for source synchronous interfaces which consist of multiple data bits and clocks. Typically, 1 channel of 7:1 LVDS interface consists of 5 LVDS pairs (1 clock, 4 data) depending on the data type it supports.

Lattice’s OpenLDI/FPD-LINK/LVDS Receiver Interface IP translates video streams from a processor with an OpenLDI/FDP-Link/LVDS interface connection to pixel clock domain, which can be used to interface with other application interface such as MIPI DSI Display Interface.


  • Compliant with Open LVDS Display Interface (OpenLDI) v0.95 specifications
  • Transmits in OpenLDI unbalanced operating mode format
  • Supports RGB888 and RGB666 video formats
  • Supports receiving in Dual Channel Flat Panel Display Link Protocol (7:1 LVDS)
  • Supports 3-4 LVDS data lanes per channel

Block Diagram



Quick Reference
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OpenLDI/FPD-LINK/LVDS-Receiver Interface IP - Lattice Radiant Software
FPGA-IPUG-02116 1.0 8/19/2020 PDF 1.7 MB
OpenLDI/FPD-LINK/LVDS Receiver Interface IP
FPGA-IPUG-02021 1.3 3/20/2020 PDF 2.4 MB

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