SubLVDS Image Sensor Receiver IP Core

Convert SubLVDS Image Sensor Video Stream to Pixel Clock Domain

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The Lattice Semiconductor SubLVDS Image Sensor Receiver IP Core converts double data rate interface to pixel clock domain. The subLVDS interface is primarily used in image sensors. It has one clock pair and more than one data pairs. The number of data pairs varies, depending on bandwidth requirement.

Features

  • 1 channel
  • Supports 4, 6, 8, or 10 data lanes from an image sensor
  • Supports 10-bit (RAW10) or 12-bit (RAW12) pixel widths
  • Supports gearing of 8 and 16. Gearing 16 option is only for 4-lane configuration
  • Can generate XVS and XHS for image sensors operating in Slave mode

Block Diagram

SubLVDS Image Sensor Receiver Block DiagramExpand Image

Resource Utilization

Number of RX Gears RX Gear Line Rate Synthesis Tool Register LUTs Fmax*
4 8 160 Mbps Synplify Pro 282 623 pixclk_o = 20 MHz
clk_p_i = 20 MHz
LSE 361 611 pixclk_o = 20 MHz
clk_p_i = 20 MHz
10 8 625 Mbps Synplify Pro 556 1116 pixclk_o = 78 MHz
clk_p_i = 20 MHz
LSE 829 1155 pixclk_o = 78 MHz
clk_p_i = 20 MHz
4 16 160 Mbps Synplify Pro 764 1968 pixclk_o = 10 MHz
clk_p_i = 20 MHz
LSE 1137 1673 pixclk_o = 10 MHz
clk_p_i = 20 MHz
4 16 1250 Mbps Synplify Pro 764 1698 pixclk_o = 78 MHz
clk_p_i = 20 MHz
LSE 1137 1673 pixclk_o = 78 MHz
clk_p_i = 20 MHz

*Note: The Fmax provided here is shown to give affirmation to the user that that target frequency for a certain bitrate is attainable. While it is possible that the maximum frequency could be higher than the one described below, the IP is bounded to limit it in order to maintain the user’s desired configuration.

Ordering Information

The SubLVDS Image Sensor Receiver IP core is available for FREE for use in Diamond design software.

For Radiant design software, the SubLVDS Image Sensor Receiver IP core must be purchased:

  Part Number
Device Family Single Design Multi-Site Subscription
Avant-E LVDS-RX-AVE-U LVDS-RX-AVE-UT LVDS-RX-AVE-US
MachXO5-NX LVDS-RX-XO5-U LVDS-RX-XO5-UT LVDS-RX-XO5-US
CertusPro-NX LVDS-RX-CPNX-U LVDS-RX-CPNX-UT LVDS-RX-CPNX-US
CrossLink-NX LVDS-RX-CNX-U LVDS-RX-CNX-UT LVDS-RX-CNX-US
Certus-NX LVDS-RX-CTNX-U LVDS-RX-CTNX-UT LVDS-RX-CTNX-US

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
SubLVDS Image Sensor Receiver IP Core - Lattice Radiant Software
FPGA-IPUG-02093 1.6 4/21/2023 PDF 770.1 KB
SubLVDS Image Sensor Receiver Submodule IP - Lattice Diamond Software
FPGA-IPUG-02023 1.3 3/20/2020 PDF 1.8 MB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

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