PCI Express

High performance, scalable, low-cost and low-power programmable solution for PCI Express

PCI Express (Peripheral Component Interconnect Express) is a high performance, scalable, well defined standard for a wide variety of computing and communications platforms. It has been defined to provide software compatibility with existing PCI drivers and operating systems.

Lattice provides customers with low-cost and low-power programmable solutions that are ready-to-use right out of the box. For PCI Express a full suite of tested and interoperable solutions is available that includes:

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Industry Leading Programmable PCI Express FPGAs

Device Certus-NX
Low-Power General Purpose FPGA
CrossLink-NX
Embedded Vision and Processing FPGA
CertusPro-NX
Advanced General Purpose FPGA
Low Cost Digital SERDES
  • PCI Express Gen1 & Gen 2 compliant with 5Gbps line speed & 2.25 Gbps for SGMII
  • PCI Express Gen1 & Gen2 compliant with 2.5Gbps & 5Gbps line speed
  • PCI Express Gen1 (2.5Gbps), Gen2 (5.0Gbps) & Gen3 (8.0Gbps) compliant
Channels in Device
  • 5 Gbps PCIe, 2.25 Gbps SGMII (GigE) and 1066 Mbps DDR3 memory
  • Supports SGMII (Gb Ethernet) Two channels (Tx/Rx) @ 1.25 Gbps
  • 625 Mbps up to 10.3125 Gbps per channel, with up to 8 channels
Complete End to End Solution
  • PIPE compliant PCS
  • PCI Express x1 and x4 soft IP available
  • PIPE compliant PCS
  • PCI Express x1 and x4 soft IP available
  • PIPE compliant PCS
  • PCI Express x1 and x4 soft IP available
Low Power
  • Up to 4x lower power vs. similar FPGAs. Up to 100x higher reliability, due to 100x lower Soft Error Rate (SER) from 28 nm FD-SOI technology.
  • Up to 75% lower power vs similar FPGAs and small form factor packaging with sizes as small as 4 mm x 4 mm.
  • Up to 4x lower power vs. similar FPGAs. Up to 100x higher reliability, due to 100x lower Soft Error Rate (SER) from 28 nm FD-SOI technology.
Low Cost FPGA Fabric
  • High end features at low cost
  • High end features at low cost
  • High end features at low cost

 


Device ECP5
Break the rules of power, size and cost in your connectivity and acceleration applications
LatticeECP3
Efficiency and innovation, squeezed into one tiny, affordable package
LatticeECP2M
Redefine the value / cost equation
Low Cost Digital SERDES
  • PCI Express Gen1 & Gen2 compliant with 2.5Gbps line speed
  • PCI Express v1.1 compliant
  • PCI Express v1.1 compliant
Channels in Device
  • Up to four channels per device: PCI Express, Ethernet (1GbE, SGMII, XAUI), and CPRI
  • Up to 16 channels per device: PCI Express, SONET/SDH, Ethernet (1GbE, SGMII, XAUI), CPRI, SMPTE 3G and Serial RapidIO
  • Up to 16 channels per device PCI Express, Ethernet (1GbE, SGMII), OBSAI, CPRI and Serial RapidIO.
Complete End to End Solution
  • PIPE compliant PCS
  • PCI Express x1 and x4 soft IP available
  • PIPE compliant PCS
  • PCI Express x1 and x4 soft IP available
  • PIPE compliant PCS
  • PCI Express x1 and x4 soft IP available
Low Power
  • 85mW Per Channel Typical @ 3.2Gbps
  • 110mW Per Channel Typical @ 3.2Gbps
  • 90mW Per Channel Typical @ 2.5Gbps
Low Cost FPGA Fabric
  • Dual channel serdes support
  • High end features at low cost
  • High end features at low cost

PCIe IP Cores

PCI Express x1 & x4 IP Core for Nexus-based FPGAs

IP Core

PCI Express x1 & x4 IP Core for Nexus-based FPGAs

The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
PCI Express x1 & x4 IP Core for Nexus-based FPGAs
PCI Express Endpoint Core

IP Core

PCI Express Endpoint Core

Provides a PCI Express x1, x2 or x4 endpoint solution from the electrical SERDES interface to the transaction layer
PCI Express Endpoint Core
PCI Express x1, x4 Root Complex Lite IP Core

IP Core

PCI Express x1, x4 Root Complex Lite IP Core

Provides a PCI Express x1 and x4 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in PCIe protocol stack
PCI Express x1, x4 Root Complex Lite IP Core
PHY Interface for PCI Express - PIPE

IP Core

PHY Interface for PCI Express - PIPE

A standard interface between a PHY device and the Media Access (MAC) layer for PCI Express (PCIe) applications
PHY Interface for PCI Express - PIPE

PCIe Evaluation Boards

CertusPro-NX Versa Board

Board

CertusPro-NX Versa Board

CertusPro-NX Versa Board supports a wide range industry standards such as MIPI, SFP+, 10 GbE, LPDDR4 and PCIe (Gen3) for rapid prototyping and testing.
CertusPro-NX Versa Board
CertusPro-NX PCIe Bridge Board

Board

CertusPro-NX PCIe Bridge Board

CertusPro-NX PCIe Bridge Board supports connectivity development platform enabling video bridge capabilities to PCIe and embedded vision type applications.
CertusPro-NX PCIe Bridge Board
Certus-NX Versa Evaluation Board

Board

Certus-NX Versa Evaluation Board

Contains a rich set of high-performance interfaces for development with the Certus-NX FPGA, including PCIe, DDR3, Ethernet PHY, cameras, PMOD and more.
Certus-NX Versa Evaluation Board
CrossLink-NX PCIe Bridge Board

Board

CrossLink-NX PCIe Bridge Board

Connectivity Development Platform Enabling Bridging of Multi-Standard I/O Interfaces to PCIe
CrossLink-NX PCIe Bridge Board
KONDOR AX Development Board

Board

KONDOR AX Development Board

ECP5 board for system design of HetNet, Industrial IoT, Cameras and Display applications
KONDOR AX Development Board

PCIe Demos

PCIe Basic Demo on Crosslink-NX PCIe Bridge Board

Demo

PCIe Basic Demo on Crosslink-NX PCIe Bridge Board

The PCIe Basic Demo allows you to control three 7 segment LEDs and manipulate the onboard memory of the FPGA through the PCIe slot.
PCIe Basic Demo on Crosslink-NX PCIe Bridge Board
PCIe Colorbar Demo for Lattice Nexus-based FPGAs

Demo

PCIe Colorbar Demo for Lattice Nexus-based FPGAs

Demo that displays a series of moving colorbars by streaming the image data using DMA transfers from the FPGA to the host system.
PCIe Colorbar Demo for Lattice Nexus-based FPGAs
PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

Demo

PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

The PCI Express DMA Throughput Demo allows to initiate DMA read and write transactions, transferring data from the host to the FPGA and vice versa.
PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs
PCIe Multifunction Demo for Lattice Nexus-based FPGAs

Demo

PCIe Multifunction Demo for Lattice Nexus-based FPGAs

Demonstrates the multifunction capabilities of the Crosslink-NX FPGA that allows access to GPIO, MDIO and I2C registers.
PCIe Multifunction Demo for Lattice Nexus-based FPGAs
Lattice ORAN™ Control Demonstration

Demo

Lattice ORAN™ Control Demonstration

Lattice ORAN provides packet authentication, encryption and decryption and support SPDM protocol over MCTP.
Lattice ORAN™ Control Demonstration

PCIe Reference Designs

Lattice ORAN™ Control Reference Design

Reference Design

Lattice ORAN™ Control Reference Design

Lattice ORAN enable secure out-of-band communication over I3C/SMBus/I2C/PCIe and provide crypto-256 and Crypto-384 services to customers through software APIs.
Lattice ORAN™ Control Reference Design
Lattice mVision MIPI Video Sensor to PCIe Bridge Reference Design

Reference Design

Lattice mVision MIPI Video Sensor to PCIe Bridge Reference Design

Reference Design that shows transfer of sensor data to the computer memory and rendering of the data as video on the computer screen using the software driver.
Lattice mVision MIPI Video Sensor to PCIe Bridge Reference Design
SLVS-EC Sensor to PCIe Bridge Reference Design

Reference Design

SLVS-EC Sensor to PCIe Bridge Reference Design

Reference Design that receives serial data from CMOS Image Sensors and convert the incoming serial data to vDMA/PCIe Subsystem data format.
SLVS-EC Sensor to PCIe Bridge Reference Design
TrellisBoard by Dave Shah

Reference Design

TrellisBoard by Dave Shah

An ECP5-based PCIe form-factor card. The board is prototyped, and available as a Reference Design on GitHub. Visit the link for more information and status.
TrellisBoard by Dave Shah