PCI Express ソリューション

High performance, scalable, low-cost and low-power programmable solution for PCI Express

PCI Express

はさまざまなコンピューティンと通信プラットホーム用の高性能でスケーラブルな、よく定義された標準です。それは、既存のPCIドライバとオペレーティング・システムとのソフトウェア互換性を提供するように定義されました。

ラティスはそのままで使用できる低コストで低消費電力電力のプログラマブル・ソリューションを提供します。PCI Express 用に用意しているテスト済みで相互接続可能なソリューションには以下を含みます。

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Industry Leading Programmable PCI Express FPGAs

シリコン

業界をリードする3つのプログラマブルPCI Expressプラットフォーム
LatticeECP3 LatticeECP2M LatticeSC
低コストデジタル SERDES
  • PCI Express v1.1 準拠
PCI Express v1.1 準拠
  • PCI Express v1.1 準拠
高性能アナログSERDES
  • PCI Express v1.1 準拠
  • PCI Express ベースの長いバックプレーンに理想的
デバイス当たり最大 16 チャネル
  • マルチプロトコル・ブリッジ機能に有効
デバイス当たり最大 16 チャネル
  • マルチプロトコル・ブリッジ機能に有効
デバイス当たり最大 32 チャネル
  • マルチプロトコル・ブリッジ機能に有効
完全なエンドツーエンド・ソリューション
  • PIPE準拠のPCS
  • PCI Express x1/x4ソフトIPを用
完全なエンドツーエンド・ソリューション
  • PIPE準拠のPCS
  • PCI Express x1/x4ソフトIPを用
完全なエンドツーエンド・ソリューション
  • 豊富なPCS機能
  • flexiMACとMACO LTSSMのハードマクロがx1やx4実装に対して全てのPHYおよびDL機能を提供
  • トランザクション層はソフト
非常に低消費電力
  • 3.2Gbpsでチャネル当たり 110mW typ.
非常に低消費電力
  • 2.5Gbpsでチャネル当たり 90mW typ.
非常に低消費電力
  • 3.125Gbpsでチャネル当たり 105mW typ.
低コストFPGAファブリック
  • 低コストでハイエンドの機能
低コストFPGAファブリック
  • 低コストでハイエンドの機能
超高性能のFPGAファブリック
  • 500MHzのブロックレベル性能

IP

ラティスはDMAとメモリコントローラを含む、PCI ExpressソフトIP及びハードIPの網羅的なポートフォリオを提供します。LatticeECP3とLatticeECP2M、および LatticeSC/Mプラットフォームをターゲットにすることによって、開発者は競合するソリューションよりもコストと、消費電力、そして実装面積を大幅に削減出来ます。

IP Port

キー

  • ソフトIP
  • リファレンス設計
  • MACO flexiMAC
  • MACO LTSSM
  • PCS
関連する IP コア
IP ベンダ LatticeECP3 LatticeECP2M LatticeSCM
PCI Expressルートコンプレックス・ライトIPコア(x1, x4) New Lattice Check Mark Check Mark  
PCI Express エンドポイント IP コア (x1, x4) Lattice Check Mark Check Mark  
DDR SDRAM コントローラ - パイプライン Lattice Check Mark Check Mark Check Mark
DDR2 SDRAM コントローラ - パイプライン Lattice Check Mark Check Mark Check Mark
SG-DMA コントローラ Lattice Check Mark Check Mark Check Mark
PCS Pipe Lattice Check Mark Check Mark  
PCI Express x1/x4 ハードIP Lattice     Check Mark
メモリコントローラ、ハード Lattice     Check Mark

PCIe IP Cores

PCI Express x1, x4 Root Complex Lite IP Core

IP Core

PCI Express x1, x4 Root Complex Lite IP Core

Provides a PCI Express x1 and x4 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in PCIe protocol stack
PCI Express x1, x4 Root Complex Lite IP Core
PCI Express for Nexus FPGAs

IP Core

PCI Express for Nexus FPGAs

The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
PCI Express for Nexus FPGAs
PCI Express for Avant and Nexus 2 FPGAs

IP Core

PCI Express for Avant and Nexus 2 FPGAs

The Lattice PCIe X8 IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
PCI Express for Avant and Nexus 2 FPGAs
PCI Express Endpoint Core

IP Core

PCI Express Endpoint Core

Provides a PCI Express x1, x2 or x4 endpoint solution from the electrical SERDES interface to the transaction layer
PCI Express Endpoint Core
PCIe High-Channel-Count DMA IP Core

IP Core

PCIe High-Channel-Count DMA IP Core

The HCC DMA IP core is a powerful PCIe DMA Engine with multiple industry standard AXI Interfaces. It is based on the Lattice PCIe HardIP.​
PCIe High-Channel-Count DMA IP Core

PCIe Evaluation Boards

CertusPro-NX Versa Board

Board

CertusPro-NX Versa Board

CertusPro-NX Versa Board supports a wide range industry standards such as MIPI, SFP+, 10 GbE, LPDDR4 and PCIe (Gen3) for rapid prototyping and testing.
CertusPro-NX Versa Board
Certus-N2 Evaluation Board

Board

Certus-N2 Evaluation Board

Certus-N2 Evaluation Board is designed for evaluating and developing with the Certus-N2 family and supports 16G Serdes, LPDDR4, PCI-Gen4.
Certus-N2 Evaluation Board
Secure Connected Motion Control Platform

Board

Secure Connected Motion Control Platform

​​This platform offers resilient connectivity, low power consumption, high performance, and robust security is increasing across various industries.​
Secure Connected Motion Control Platform
Certus-NX 65K Development Board

Board

Certus-NX 65K Development Board

Certus-NX 65K Development Board features the Certus NX-65 device in a 486-ball caBGA package that offers variety of features to expand the usablity with Arduino, Versa, Raspberry, PMOD, Aardvark, header and 1x PCIe(Gen2) Channel.
Certus-NX 65K Development Board
MachXO5-65T Development Board

Board

MachXO5-65T Development Board

The MachXO5-65T Development Board features the LFMXO5-65T device in a 484-ball caBGA package. The board offers a variety of features to expand the usability of the MachXO5-NX-65T with Arduino, Versa, Raspberry Pi, PMOD, and AARDVARK header.
MachXO5-65T Development Board

PCIe Demos

PCIe Basic Demo for Lattice Nexus-based FPGAs

Demo

PCIe Basic Demo for Lattice Nexus-based FPGAs

The PCIe Basic Demo allows you to control three 7 segment LEDs and manipulate the onboard memory of the FPGA through the PCIe slot.
PCIe Basic Demo for Lattice Nexus-based FPGAs
PCIe Colorbar Demo for Lattice Nexus-based FPGAs

Demo

PCIe Colorbar Demo for Lattice Nexus-based FPGAs

PCIe Colorbar Demo displays a series of moving colorbars by streaming the image data using DMA transfers from the FPGA to the host system.
PCIe Colorbar Demo for Lattice Nexus-based FPGAs
PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

Demo

PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

The PCI Express DMA Throughput Demo allows to initiate DMA read and write transactions, transferring data from the host to the FPGA and vice versa.
PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs
PCIe Multifunction Demo for Lattice Nexus-based FPGAs

Demo

PCIe Multifunction Demo for Lattice Nexus-based FPGAs

Demonstrates the multifunction capabilities of the Crosslink-NX FPGA that allows access to GPIO, MDIO and I2C registers.
PCIe Multifunction Demo for Lattice Nexus-based FPGAs
Demo for Lattice ORAN Secure Sync for IEEE 1588 PTP

Demo

Demo for Lattice ORAN Secure Sync for IEEE 1588 PTP

Demo for Lattice ORAN Secure Sync show how Lattice FPGA w/ soft IPs can support tight & secure synchronization using 1588 PTP & ITU profiles for Telecom.
Demo for Lattice ORAN Secure Sync for IEEE 1588 PTP

PCIe Reference Designs

Lattice ORAN™ 1.0 Security Reference Design

Reference Design

Lattice ORAN™ 1.0 Security Reference Design

Lattice ORAN enable secure out-of-band communication over I3C/SMBus/I2C/PCIe and provide crypto-256 and Crypto-384 services to customers through software APIs.
Lattice ORAN™ 1.0 Security Reference Design
5G Small Cell PCIe to JESD204B Bridge Reference Design

Reference Design

5G Small Cell PCIe to JESD204B Bridge Reference Design

5G Mid-Power Integrated Small Cell, reference platform is a comprehensive development board tailored for 5G baseband processors and transceiver frontends.
5G Small Cell PCIe to JESD204B Bridge Reference Design
Lattice ORAN IEEE 1588 PTP Secure Sync Reference Design

Reference Design

Lattice ORAN IEEE 1588 PTP Secure Sync Reference Design

Lattice ORAN 1.1 RD shows how to provide ultra-reliable time synchronization & phase alignment for delivering timing accuracy in 5G ORAN networks.
Lattice ORAN IEEE 1588 PTP Secure Sync Reference Design
Lattice mVision MIPI Video Sensor to PCIe Bridge Reference Design

Reference Design

Lattice mVision MIPI Video Sensor to PCIe Bridge Reference Design

Reference Design that shows transfer of sensor data to the computer memory and rendering of the data as video on the computer screen using the software driver.
Lattice mVision MIPI Video Sensor to PCIe Bridge Reference Design
SLVS-EC Sensor to PCIe Bridge Reference Design

Reference Design

SLVS-EC Sensor to PCIe Bridge Reference Design

SLVS-EC to PCIe reference design allows the quick interface to receive serial data from CMOS Image Sensors & convert to DMA/PCIe Subsystem data format.
SLVS-EC Sensor to PCIe Bridge Reference Design