Guidance Systems

Meet mission requirements with low power and high reliability advantages of Lattice FPGAs

Related Applications


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For over 25 years, , Lattice has enabled leading-edge guidance systems with a wide range of high reliability, SWAP-C optimized products that meet today’s security, longevity, and extreme environment challenges. Engineers at leading defense contractors rely on our deep system-level knowledge, collaborative spirit, local support, and design resources to meet the most stringent design requirements.

Lattice COTS FPGAs provide the flexibility to adapt to the requirements of next generation precision guided systems with low power actuator control, sensor fusion, and signal processing solutions. The latest Lattice Nexus platform features industry leading low power and high reliability to meet the challenging requirements of next generation guidance platforms.

Key Lattice FPGA Features & Benefits

  • Superior low power consumption and thermal performance compared to other FPGAs, enabling longer missions, and simplifying thermal management
  • Industry leading small form factor FPGAs, optimized for highest I/O density, connect to more sensors, creating a high-fidelity situational awareness
  • Lowest soft error rate (SER) in its class and highest latch-up immunity to maximize integrity of ground-based and airborne systems
  • Enables low latency, deterministic, instant-on start-up with initial I/O configuration in less than 3 ms and full device configuration in as little as 8 ms

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Example Applications

Actuator controlExpand Image

Actuator Control

  • Single-chip non-volatile FPGAs with 2ms bitstream verification, authentication and boot-up time
  • Embedded A/D converters for sensor fusion, feedback and sensing
  • Packages as small as 6x6 mm, and in ball-pitch options of 0.5 and 0.8 mm
Trigger SystemsExpand Image

Trigger

  • Critical bitstream verification and safety compliance
  • ECDSA bitstream authentication, coupled with robust AES-256 encryption
  • Robust flash-based FPGAs ideal for sensor processing and control
TelemetryExpand Image

Telemetry

  • Power efficient, highly reliable system control and monitoring
  • Optimum integration level with embedded MCU and ADCs
  • Utmost control and flexibility in sense and control of rea-time data

Reference Designs

Sensor Interfacing and Preprocessing

Reference Design

Sensor Interfacing and Preprocessing

Aggregates data from multiple I2C interfaces and performs preprocessing like buffering, timestamping and complex event triggering based on data analysis.
iCE40 UltraPlus, iCE40 Ultra / UltraLite, iCE40 LP/HX 
Accelerometer, Compass, Gyroscope, I2C, IrDA, Pressure Sensor, Signal Aggregation, SPI, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Guidance Systems, Space 
Sensor Interfacing and Preprocessing
Simple Sigma-Delta ADC

Reference Design

Simple Sigma-Delta ADC

Implements an Analog-to-Digital (ADC) using on-FPGA differntial LVDS inputs (or inexpensive analog comparitor). Save cost by eliminating external ADC devices.
MachXO, MachXO2, LatticeXP2, iCE40 UltraPlus 
ADC/DAC, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Guidance Systems 
Simple Sigma-Delta ADC
SPI Slave to PWM Generation

Reference Design

SPI Slave to PWM Generation

Sets the frequency and duty cycle of a PWM (Pulse-Width Modulator) using data from an external SPI master.
MachXO2, iCE40 UltraPlus 
SPI, PWM, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Guidance Systems, Space 
SPI Slave to PWM Generation
I2C Slave Peripheral using Embedded Function Block

Reference Design

I2C Slave Peripheral using Embedded Function Block

Ready to use RTL code segment that implements intuitive interface between an external I2C master and the MachXO2 internal registers or memory extension in XO2
MachXO2, MachXO3 
Bus Controllers, I2C, TOR Switch, Guidance Systems 
I2C Slave Peripheral using Embedded Function Block
ADC Interface

Reference Design

ADC Interface

Interfaces with the Texas Instruments (TI) ADS64XX family of ADCs via LatticeECP3 FPGA high-speed LVDS I/O
LatticeECP3, LatticeECP2/M 
ADC/DAC, Guidance Systems, Space 
ADC Interface
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IP Cores

Byte to Pixel Converter IP Core

IP Core

Byte to Pixel Converter IP Core

Lattice Semiconductor Byte-to-Pixel Converter IP converts CSI-2/DSI standard based video payload packets from D-PHY Receiver Module output to pixel format
CrossLink, CrossLinkPlus, CrossLink-NX, Certus-NX, CertusPro-NX, Avant-E, MachXO5-NX 
MIPI, Modular MIPI/D-PHY, Parallel Video, Video Tx/Rx, Lattice mVision, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Guidance Systems, Automotive, Space 
Byte to Pixel Converter IP Core
CSI-2/DSI D-PHY Transmitter IP Core

IP Core

CSI-2/DSI D-PHY Transmitter IP Core

The CSI-2/DSI D-PHY Transmitter Submodule IP is for applications requiring D-PHY transmitter in the FPGA logic & supports both high-speed & low power modes
CrossLink, CrossLinkPlus, CrossLink-NX, Certus-NX, CertusPro-NX, Avant-E, MachXO5-NX 
CSI-2, DSI, MIPI, Modular MIPI/D-PHY, Video Tx/Rx, Lattice mVision, AR / VR & Drones, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Guidance Systems, Automotive, Space 
CSI-2/DSI D-PHY Transmitter IP Core
Pixel to Byte Converter IP Core

IP Core

Pixel to Byte Converter IP Core

Converts one, two, four, six, eight, or ten pixels per pixel clock into MIPI D-PHY byte packet compatible format
CrossLink, CrossLinkPlus, CrossLink-NX, Certus-NX, CertusPro-NX, Avant-E, MachXO5-NX 
CSI-2, MIPI, Modular MIPI/D-PHY, Parallel Video, Video Tx/Rx, Lattice mVision, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Guidance Systems, Automotive 
Pixel to Byte Converter IP Core
UART 16550 IP Core

IP Core

UART 16550 IP Core

Configurable UART port. Compatible with PC16550D. 7 or 8 bit data width, 1, 1.5, 2 stop bits for Tx. Multiple parity and baud rate options.
iCE40 UltraPlus, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX 
Bus Controllers, UART, TOR Switch, Guidance Systems, Automotive, Space 
UART 16550 IP Core
PCI Express x1, x4 Root Complex Lite IP Core

IP Core

PCI Express x1, x4 Root Complex Lite IP Core

Provides a PCI Express x1 and x4 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in PCIe protocol stack
ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M 
Connectivity IP Suite, PCIe, PCIe IP Suite, Guidance Systems, Automotive 
PCI Express x1, x4 Root Complex Lite IP Core
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Development Kits & Boards

ECP5 Versa Development Kit

Board

ECP5 Versa Development Kit

Evaluate and develop for key connectivity features of the ECP5 FPGA, including PCI Express, Gigabit Ethernet, DDR3 and generic SERDES, includes numerous demos.
ECP5 / ECP5-5G 
Data Communication, Ethernet, PCIe, SERDES, SMA, Versa Connector, DDR SDRAM, TOR Switch, Guidance Systems 
ECP5 Versa Development Kit
ECP5-5G Versa Development Kit

Board

ECP5-5G Versa Development Kit

Evaluate and develop for key connectivity features of the ECP5-5G FPGA, including PCI Express, Gigabit Ethernet, DDR3 and 5G SERDES, includes numerous demos.
ECP5 / ECP5-5G 
Data Communication, Ethernet, PCIe, SERDES, SMA, Versa Connector, DDR SDRAM, Guidance Systems 
ASC Bridge Board

Board

ASC Bridge Board

Interface with multiple (1-3) L-ASC10 Evaluation boards for rapid prototyping, development and testing of Power Management tasks
Platform Manager 2 & L-ASC10 
Mixed-Signal, Power Management, RS-232, Versa Connector, TOR Switch, Guidance Systems 
ASC Bridge Board
L-ASC10 Breakout Board

Board

L-ASC10 Breakout Board

A versatile hardware platform for evaluating and designing with L-ASC10 devices. Connect and control with FPGAs via the ASC Bridge board.
Platform Manager 2 & L-ASC10 
Mixed-Signal, Power Management, RS-232, TOR Switch, Guidance Systems 
L-ASC10 Breakout Board
POWR1014A Breakout Board

Board

POWR1014A Breakout Board

A simple low-cost board that provides complete I/O access to the Power Manager II (POWR1014A)+LEDs, Prototyping area and more.
Power Manager II 
Breakout, Mixed-Signal, Power Management, TOR Switch, Guidance Systems 
POWR1014A Breakout Board
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Demos

Power Sequencing with Fault Logging Demo

Demo

Power Sequencing with Fault Logging Demo

Uses L-ASC10 to monitor, sequence four separate Power Planes from a central control point. Logs faults with timestamps. Expandable.
Platform Manager 2 & L-ASC10, MachXO3 
Mixed-Signal, Power Management, TOR Switch, Guidance Systems, 5G 
Power Sequencing with Fault Logging Demo

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-02076 1.7 5/9/2023 PDF 522 KB
Multi-Boot User Guide for Nexus Platform
FPGA-TN-02145 1.5 4/18/2023 PDF 751.6 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-02076 1.7 5/9/2023 PDF 522 KB
Multi-Boot User Guide for Nexus Platform
FPGA-TN-02145 1.5 4/18/2023 PDF 751.6 KB
Implementing JOTP-051-Compliant Safety Features in Lattice FPGAs
FPGA-TN-02150 1.1 3/15/2021 PDF 855.2 KB

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