Smart Munitions

Increased Autonomy with Sensor Fusion

Related Products

Launched from various platforms, smart munitions are advanced systems that rely on sophisticated sensors and signal processing to offer a wide variety of functions and features from GPS-denied environments to autonomous detection and classification. Lattice FPGAs implement complex signal processing algorithms including object detection and classification and enable seamless sensor connectivity and management of data secure data flow to a wide variety of sensors and handle secure, anti-tamper communication and control. 

  • Low power FPGAs to meet extended temperature and other harsh environmental constraints
  • Industry leading fast, secure boot with state of the art security and robust encryption to meet domain specific safety, security and reliability requirements
  • Sophisticated tool flow with redundancy, isolation design flow in support of Design Assurance Levels.

Features

  • Lattice FPGAs with small form factor, low power deliver a robust sensor and signal processing solution with adaptable parallel / serial interfaces and high speed transceiver connections to analog front ends while meeting SWaP-C requirements.
  • Industry leading advanced security features including AES256-GCM, ECDSA 256-521 & RSA 2048-4096 with post quantum resilience, anti-tamper and hardened PUF to secure bitstream and user data and support upgradability to tackle future needs and evolving threats.
  • State of the art security features including industry’s fastest secure boot and hardware security measures enable robust security protocols withing the constrained environment and reliable operation at extremely high speeds.

Jump to

Example-Applications

Actuator Control

  • Single-chip non-volatile FPGAs with 2ms bitstream verification, authentication and boot-up time
  • Embedded A/D converters for sensor fusion, feedback and sensing
  • Packages as small as 6x6 mm, and in ball-pitch options of 0.5 and 0.8 mm 

Telemetry

  • Power efficient, highly reliable system control and monitoring
  • Optimum integration level with embedded MCU and ADCs
  • Utmost control and flexibility in sense and control of rea-time data

Trigger

  • Critical bitstream verification and safety compliance
  • ECDSA bitstream authentication, coupled with robust AES-256 encryption
  • Robust flash-based FPGAs ideal for sensor processing and control

Reference Design

Redundant Power Supply Management

Reference Design

Redundant Power Supply Management

Uses a Lattice Power Manager II device to achieve Redundant Power Supply Management using the power supply OR’ing technique
Redundant Power Supply Management
SPIスレーブからPWM生成

Reference Design

簡易シグマデルタ ADC

Reference Design

簡易シグマデルタ ADC

Implements an Analog-to-Digital (ADC) using on-FPGA differntial LVDS inputs (or inexpensive analog comparitor). Save cost by eliminating external ADC devices.
簡易シグマデルタ ADC
組込み機能ブロックを使ったI2Cスレーブ周辺機器

Reference Design

組込み機能ブロックを使ったI2Cスレーブ周辺機器

Ready to use RTL code segment that implements intuitive interface between an external I2C master and the MachXO2 internal registers or memory extension in XO2
組込み機能ブロックを使ったI2Cスレーブ周辺機器

Demo

Power Sequencing with Fault Logging Demo

Demo

Power Sequencing with Fault Logging Demo

Uses L-ASC10 to monitor, sequence four separate Power Planes from a central control point. Logs faults with timestamps. Expandable.
Power Sequencing with Fault Logging Demo

IP Cores

FFT Compiler IP Core

IP Core

FFT Compiler IP Core

The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT.
FFT Compiler IP Core
FIR Filter IP Core

IP Core

FIR Filter IP Core

This IP core is a widely configurable, multi-channel FIR filter, implemented using high performance sysDSP™ blocks available in Lattice devices.
FIR Filter IP Core
PCI Express x1, x4 Root Complex Lite IP Core

IP Core

PCI Express x1, x4 Root Complex Lite IP Core

Provides a PCI Express x1 and x4 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in PCIe protocol stack
PCI Express x1, x4 Root Complex Lite IP Core

Development Kits & Boards

ECP5 Versa 開発キット

Board

ECP5 Versa 開発キット

ECP5 Versa開発キットでPCI Express,、Gigabit Ethernet、DDR3、汎用Serdesパフォーマンスを含むECP5の主要機能の迅速な評価が可能
ECP5 Versa 開発キット
ECP5-5G Versa開発キット

Board

ECP5-5G Versa開発キット

PCI Express、Gigabit Ethernet、DDR3、ECP5-5G SERDESの性能を評価する
L-ASC10ブレークアウトボード

Board

L-ASC10ブレークアウトボード

L-ASC10デバイスを評価および設計する多才なハードウェアプラットフォームです。 このボードは、プラットフォームマネージャー 2開発キットとともに動作するように設計されています。
L-ASC10ブレークアウトボード

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-02076 2.3 10/13/2025 PDF 806.2 KB
Multi-Boot User Guide for Nexus Platform
FPGA-TN-02145 2.4 8/27/2025 PDF 1.4 MB
Implementing JOTP-051-Compliant Safety Features in Lattice FPGAs
FPGA-TN-02150 1.1 3/15/2021 PDF 855.2 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-02076 2.3 10/13/2025 PDF 806.2 KB
Multi-Boot User Guide for Nexus Platform
FPGA-TN-02145 2.4 8/27/2025 PDF 1.4 MB
Implementing JOTP-051-Compliant Safety Features in Lattice FPGAs
FPGA-TN-02150 1.1 3/15/2021 PDF 855.2 KB

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