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  • MIPI-to-Parallel and Parallel-to-MIPI Bridges Reference Design

    Reference Design

    MIPI-to-Parallel and Parallel-to-MIPI Bridges Reference Design

    ​​The design allows quick interface for a processor with a MIPI DSI with an RGB interface, or camera with MIPI CSI-2 to a processor with parallel interface​
    MIPI-to-Parallel and Parallel-to-MIPI Bridges Reference Design
  • Human Face Identification Reference Design

    Reference Design

    Human Face Identification Reference Design

    Uses a Convolutional Neural Network in the ECP5 FPGA to detect a human face, and match to known registered faces. Can be adapted to work with any other object.
    Human Face Identification Reference Design
  • Human Presence Detection

    Reference Design

    Human Presence Detection

    Uses Lattice sensAI IP to continuously search for the presence of a human and reports results. Can be adapted to detect any other object.
    Human Presence Detection
  • Object Counting AI

    Reference Design

    Object Counting AI

    An example object counting application based on the Lattice sensAI stack. Includes SPI, DDR IP blocks, ISP engine, 8 CNN engines and a counting / overlay engine
    Object Counting AI
  • CertusPro-NX N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation

    Reference Design

    CertusPro-NX N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation

    Modular MIPI/D-PHY Reference Design - Multiple channel image data concatenated horizontally line by line and offers up to eight-channel aggregation.
    CertusPro-NX N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation
  • SLVS-EC to MIPI CSI-2 Reference Design

    Reference Design

    SLVS-EC to MIPI CSI-2 Reference Design

    Modular MIPI/D-PHY Reference Design - Support advance camera and display interconnections in mobile devices that enable higher performance sensor with optimized power.
    SLVS-EC to MIPI CSI-2 Reference Design
  • MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge Reference Design

    Reference Design

  • I2C Bus Master

    Reference Design

    I2C Bus Master

    Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
    I2C Bus Master
  • I2C Master - WISHBONE Compatible

    Reference Design

    I2C Master - WISHBONE Compatible

    Based on the OpenCores I2C master core, this Reference Design provides a bridge between the I2C and WISHBONE bus
    I2C Master - WISHBONE Compatible
  • RGB LED Reference Design

    Reference Design

    RGB LED Reference Design

    A complete RGB LED design that controls the color, blinking rate, brightness and breathing of an RGB LED.
    RGB LED Reference Design
  • Simple Sigma-Delta ADC

    Reference Design

    Simple Sigma-Delta ADC

    Implements an Analog-to-Digital (ADC) using on-FPGA differntial LVDS inputs (or inexpensive analog comparitor). Save cost by eliminating external ADC devices.
    Simple Sigma-Delta ADC
  • SPI Master Controller

    Reference Design

    SPI Master Controller

    Implements a SPI Master Controller in VHDL and uses an iCE40™ ultra low density FPGA and can be targeted to other iCE40 family members.
    SPI Master Controller
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