SPI Master Controller

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Reference Design LogoThe Serial Peripheral Interface (SPI) bus provides an industry standard interface between processors and other devices. This reference design documents a SPI Master Controller designed to provide an interface between a generic processor with parallel bus interface and external SPI devices. The SPI Master Controller can communicate with multiple off-chip SPI ports.

The data size of the SPI bus can be configured to either 16 or 32 bits. The design can also to be configured to use an internal FIFO or not. The SPI Master Controller design supports all modes of CPOL and CPHA (00, 01, 10 and 11).

This design uses three pins (clock, data in and data out) plus one select for each slave device. A SPI is a good choice for communicating with low-speed devices that are accessed intermittently and transfer data streams rather than reading and writing to specific addresses. A SPI is an especially good choice if we can take advantage of its full-duplex capability for sending and receiving data at the same time.

This reference design is implemented in VHDL. The Lattice iCECube2™ Place and Route tool integrated with the Synplify Pro synthesis tool is used for the implementation of the design. The design uses an iCE40™ ultra low density FPGA and can be targeted to other iCE40 family members.


  • Four SPI slave select lines based on address
  • Provision for easy integration of any processor interface
  • Compile time configurable features
    • CPOL and CPHA modes – 00, 01, 10, 11
    • Configurable SCLK period
    • Configurable setup, hold and time interval between two SPI transactions
  • Parameterized data width
  • User-configurable read and write data FIFOs
  • P-XACT version 1.2 compliant

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Block Diagram

SPI Master Controller Block Diagram

Performance and Size

Device Family Utilization (LUTs) Language fMAX (MHz) I/O Pins Architectural
iCE40™ 360 VHDL 125 86 N/A

Performance and resource utilization characteristics are generated using iCE-40LP1K-CM121 with iCEcube2 design software.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.


Technical Resources
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SPI Master Controller - Source Code
RD1141 1.0 10/12/2012 ZIP 866.8 KB
SPI Master Controller - Documentation
FPGA-RD-02174 1.1 2/5/2021 PDF 683.1 KB

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