The Serial Peripheral Interface (SPI) bus provides an industry standard interface between processors and other devices. This reference design documents a SPI Master Controller designed to provide an interface between a generic processor with parallel bus interface and external SPI devices. The SPI Master Controller can communicate with multiple off-chip SPI ports.
The data size of the SPI bus can be configured to either 16 or 32 bits. The design can also to be configured to use an internal FIFO or not. The SPI Master Controller design supports all modes of CPOL and CPHA (00, 01, 10 and 11).
This design uses three pins (clock, data in and data out) plus one select for each slave device. A SPI is a good choice for communicating with low-speed devices that are accessed intermittently and transfer data streams rather than reading and writing to specific addresses. A SPI is an especially good choice if we can take advantage of its full-duplex capability for sending and receiving data at the same time.
This reference design is implemented in VHDL. The Lattice iCECube2™ Place and Route tool integrated with the Synplify Pro synthesis tool is used for the implementation of the design. The design uses an iCE40™ ultra low density FPGA and can be targeted to other iCE40 family members.