莱迪思解决方案

Reference Design

GHRD/GSRD参考设计

黄金硬件和软件参考设计（GSRD）包括了使用基于CertusPro-NX Versa开发板开发各种应用所需的组件。

CertusPro-NX, Avant-E 

GHRD, GSRD, RISC-V, AXI4, MPMC, Lattice Automate, Defense 

Reference Design

USB到I/O聚合和桥接参考设计

USB到I/O桥接参考设计为支持USB的FPGA提供即插即用外设扩展，还支持从USB到I2C、SPI和GPIO的信号协议转换。

CrossLink-NX 

USB, USB2, USB3, I2C, SPI, JTAG, LVDS, SLVS, FTDI 

Reference Design

Close Loop BLDC Motion Control Reference Design

Implementation of Industrial high-end encoder on real-time position feedback for speed control in the Closed-loop BLDC motor control system

Certus-NX 

BLDC, RISC-V, Avionics 

Reference Design

Configuration Access through CONFIG LMMIC Primitive Reference Design

This reference design demonstrates using the Lattice memory mapped interface (LMMI) host logic to drive the LMMI interface of the CONFIG_LMMIC primitive.

Avant-X 

CONFIG_LMMIC, LMMI, CFG 

Reference Design

CrossLinkU-NX UVC Streaming Reference Design

UVC streaming Reference Design provides a template for video streaming from camera sensor over the USB hard IP in the CrossLinkU-NX device to a USB host.

CrossLink-NX 

UVC, MIPI, USB, Video Streaming, Avionics 

Reference Design

Customizable HSB Sensor Interfaces Reference Design

The design specifically targets MIPI CSI-2 camera sensors and offers a flexible architecture capable of integrating multiple camera inputs based on system requirements.

CertusPro-NX 

HSB, Sensor Interface, MIPI, CSI-2, Customizable HSB 

Reference Design

EtherCAT with Single-Axis Motor Control Reference Design

Ethernet for Control Automation Technology (EtherCAT) with Motor Control reference design comprises a complete RISC-V embedded system integrated with the Beckhoff EtherCAT SubDevice IP and the Lattice FOC Motor Control IP.

CertusPro-NX 

EtherCAT, Motor Control, ESC, FOC 

Reference Design

FOC Motor Control Reference Design

The Field-Oriented Control (FOC) Motor Control reference design comprises a complete RISC-V embedded system integrated with the FOC Motor Control IP.

Certus-NX 

FOC, RISC-V, MATLAB, UART 

Reference Design

Holoscan Sensor Bridge Reference Design

This design integrates seamlessly with the NVIDIA Holoscan Sensor Bridge, offering configurable FPGA IP, system control, and a full-stack data acquisition pipeline for IGX Orin and Orin AGX platforms.

CertusPro-NX 

HSB, Sensor Interface, MIPI, CSI-2, NVIDIA Holoscan 

Reference Design

Lattice ORAN™控制参考设计

莱迪思ORAN支持通过I3C/SMBus/I2C/PCIe实现安全的带外通信，并通过软件API为客户提供Crypto-256和Crypto-384加密服务。

CertusPro-NX 

5G, PCIe, SPI, Lattice ORAN 

Reference Design

Lattice Sentry 4.0 SCM和HPM CPLD参考设计

这是一个Sentry 4.0服务器解决方案平台的安全控制模块（SCM）和主机平台模块（HPM）的CPLD设计模板。

MachXO3D, MachXO5-NX 

SCM, HPM, CPLD, Lattice Sentry, Security, Defense, LTPI, MPESTI, SGPIO, eSPI, OCP 

Reference Design

MIPI CSI-2 to PCIe Reference Design

CertusPro™‑NX MIPI CSI‑2 to PCIe reference design streams camera video to a PC via DMA on the Versa Board, with Linux drivers and capture‑to‑display demo.

CertusPro-NX 

CSI, FPGA, MIPI, OS, PCIe, Video Tx/Rx, AR / VR & Drones, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Automotive, Lattice mVision, Lattice Automate, Nexus PCIe 

Reference Design

MIPI CSI-2 to USB UVC Reference Design

CrosslinkU™NX MIPI CSI2 to USB reference design enables unified camera video streaming using the device’s integrated USB hard IP.

CertusPro-NX 

UVC, MIPI, USB, Video Streaming, Avionics 

Reference Design

MIPI CSI-2转HDMI参考设计

MIPI CSI-2转HDMI参考设计包括了仿真设计所需的可综合的MIPI-HDMI内核设计和激励发生器、检查器和测试平台。

Avant-E 

Lattice mVision, MIPI, HDMI, CSI-2, I2C 

Reference Design

Mixed Mode PCIe and TSEMAC Reference Design

This reference design describes how to set up and run the Mixed Mode PCI Express (PCIe) basic demo and Tri-Speed Ethernet (TSE) in loopback mode using devices built on the CertusPro™-NX FPGA.

CertusPro-NX 

PCIe, TSEMAC 

Reference Design

MPESTI Initiator Reference Design

The design specifically targets MIPI CSI-2 camera sensors and offers a flexible architecture capable of integrating multiple camera inputs based on system requirements.

Avant-E, MachXO5-NX, MachXO3, MachXO3D 

MPESTI, UART, APB, AHB, RISC-V, OCP 

Reference Design

Multi-Boot Reference Design

Multi-Boot mode supports booting from up to 6 patterns that reside in an external SPI flash device, up to 3 patterns for MachXO5-NX internal flash memory.

MachXO5-NX, CrossLink-NX, CertusPro-NX, Certus-NX 

Multi-boot, SPI 

Reference Design

POS PHY Level 3链路

Enables real-time detection, classification, and tracking of multiple objects in images and video streams at the edge.

CertusPro-NX 

D-PHY, OSPI, PCIe, USB, SPI, I2C, AXI, APB, Lattice sensAI 

Reference Design

POS PHY Level 3链路

Enables real-time identification and classification of defects in manufacturing, assembly, and inspection processes at the edge.

CertusPro-NX 

D-PHY, OSPI, PCIe, USB, SPI, I2C, AXI, APB, Lattice sensAI 

Reference Design

SEDC Controller Reference Design

Soft Error Detection (SED) and Soft Error Correction (SEC) reference design implements a state machine controller that interfaces with the SEDC Controller IP to enable the soft error detection/correction (SEDC) function, which can be used to detect and correct static random access memory (SRAM) errors.

Avant-E 

SED, SEC, SEDC, LMMI, SRAM