Mixed Mode PCIe and TSEMAC Reference Design

Enable PCIe & TSE Comms with Dual Function Setup

This reference design describes how to set up and run the Mixed Mode PCI Express (PCIe) basic demo and Tri-Speed Ethernet (TSE) in loopback mode using devices built on the CertusPro™-NX FPGA.

The demo is targeted for CertusPro-NX Versa Evaluation Board, which features the CertusPro-NX FPGA in the LFG672 package. The above-mentioned FPGAs are built on the Nexus™ FPGA platform using low-power 28 nm FD-SOI technology.

Features

  • Read and write to onboard memory of the CertusPro-NX FPGA through PCIe
  • Three 7-segment LED control using Lattice Nexus FPGA through PCIe Interface
  • Packet generator and checker implemented through TSEMAC through external loopback

Block Diagram

Mixed RD Block DiagramExpand Image

Mixed Mode PCIe and TSEMAC Reference Design Block Diagram for CertusPro-NX

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Mixed Mode PCIe and TSEMAC Reference Design - Source Code
4/15/2026 ZIP 68 MB
Mixed Mode PCIe and TSEMAC Reference Design - User Guide
FPGA-RD-02313 1.0 4/15/2026 PDF 2.5 MB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

ABOUT LATTICE

SALES

SUPPORT

FOLLOW