​​Modern Avionics platforms with Assurance and Security

Enabling Airborne platform with Functional Safety certified and DO-254 solutions

Related Products

The Avionics industry is a realm of exceptional standards and unyielding reliability. Modern Avionics systems with electronic controls and heightened security requirements must provide advanced functionality while maintaining safety, reliability and assured performance. Leveraging the strength of our ecosystem, Lattice offers a comprehensive DO-254 solution with Intellectual property and tool flow to reduce the risk and accelerate time to market of avionics platforms. Lattice supports functional safety for industrial IEC 61508 and automotive ISO 26262, with TÜV certified design flows that enable applications to be certified. The certified tool chain spans Lattice Diamond and Radiant (including Synplify and ModelSim), with workflows aligned to DO 254 and options such as TMR.

  • Low power FPGAs to meet stringent MIL-STD environment tests and assurance
  • Ruggedized, leaded packages with reliable operation in extreme environments
  • Industry leading fast, secure boot with state of the art security and robust encryption to meet domain specific safety, security and reliability requirements 
  • Sophisticated tool flow with redundancy and isolation design flow in support of Design Assurance Levels

Key Lattice FPGA Features & Benefits

  • From non-volatile FPGAs to mid-range FPGA that scales up to 637 Logic Cells and 28 multi-protocol transceivers optimized for edge connectivity/sensing connectivity, signal conditioning/pre-processing, and safe/deterministic control.
  • Industry leading advanced security features including AES256-GCM, ECDSA 256-521 & RSA 2048-4096 with post quantum resilience, anti-tamper and hardened PUF to secure bitstream and user data and support upgradability to tackle future needs and evolving threats. 
  • Design tools offer latest advancements in scripting, design partitioning, timing analysis, high speed interface debug and third party tools integration for synthesis including TMR, simulation and verification.

Jump to

Videos

Video Thumbnail
Expand Video

LDC24 Demo - Logic Fruit Technologies Inc. ARINC 818-3 IP

Leaded Package Overview

Lattice offers leaded packaging services to eliminate the risk for tin-whisker and to improve reliability in presence of high shock and vibration applications.

Lattice Packages Wirebond Flip Chip
Wafer Pad or Bump Lead free Lead free
Substrate bump or pad finish Lead free Lead free
Caps No Caps No Caps
Substrate Solder Balls Leaded Leaded
Package Reflow Leaded Leaded

Known Good Die Product Overview

Lattice offers a wide variety of known good die products, tested to full data sheet specification within the specified temperature range with full traceability for each die shipped.

Family Logic Density Test Method Programmability Temperature Range
LatticeECP3 150K Known Good Die Volatile -40 C to 125 C
LatticeXP2 40K Good Die Non-volatile -40 C to 125 C
ECP5 85K Known Good Die Volatile -40 C to 125 C
MachXO3 10K Known Good Die Non-volatile -40 C to 105 C
Avant 637K Known Good Die Volatile -40C to +125C
Certus-NX 39K Known Good Die Volatile -40C to +125C
CertusPro-NX 96K Known Good Die Volatile -40C to +125C
CrossLink-NX 39K Known Good Die Volatile -40C to +125C

Reference Designs

Close Loop BLDC Motion Control Reference Design

Reference Design

Close Loop BLDC Motion Control Reference Design

Implementation of Industrial high-end encoder on real-time position feedback for speed control in the Closed-loop BLDC motor control system
Close Loop BLDC Motion Control Reference Design
CrossLinkU-NX UVC Streaming Reference Design

Reference Design

CrossLinkU-NX UVC Streaming Reference Design

UVC streaming Reference Design provides a template for video streaming from camera sensor over the USB hard IP in the CrossLinkU-NX device to a USB host.
CrossLinkU-NX UVC Streaming Reference Design
Lattice QSPI to NXP MPU Interface Reference Design

Reference Design

Lattice QSPI to NXP MPU Interface Reference Design

This Lattice and NXP joint solution is designed to implement FlexSPI communication and expedite deployment using the Lattice ECP5 Evaluation Board.
Lattice QSPI to NXP MPU Interface Reference Design
DisplayPort & Video Scaler Reference Design

Reference Design

DisplayPort & Video Scaler Reference Design

The Lattice Drive DisplayPort & Video Scaler Reference Design implements easy evaluation of various DisplayPort interface.
DisplayPort & Video Scaler Reference Design
MIPI CSI-2 to Ethernet Reference Design

Reference Design

MIPI CSI-2 to Ethernet Reference Design

The MIPI CSI-2 to Ethernet reference design is an advanced system that integrates two camera sensors with each Lattice Avant™ Versa board.
MIPI CSI-2 to Ethernet Reference Design

IP Cores

10G Ethernet IP Core

IP Core

10G Ethernet IP Core

The Lattice 10G Ethernet IP Core supports the ability to transmit and receive data between a host processor and an Ethernet network.
10G Ethernet IP Core
25G Ethernet IP Core

IP Core

25G Ethernet IP Core

The Lattice Semiconductor 25G Ethernet IP Core supports the ability to transmit and receive data between a host processor and an Ethernet network.
25G Ethernet IP Core
Image Signal Processing IP Cores Suite

IP Core

Image Signal Processing IP Cores Suite

The Lattice mVision ISP IP Core implements ISP pipelines for image quality enhancements in embedded designs based on Lattice FPGA devices.
Image Signal Processing IP Cores Suite
MACsec AES256-GCM, High-speed (XIP1213H)

IP Core

MACsec AES256-GCM, High-speed (XIP1213H)

The high-speed MACsec IP core implements the MACsec protocol as standardized in IEEE 802.1AE-2018, defining a security infrastructure for OSI model Layer 2 traffic.
MACsec AES256-GCM, High-speed (XIP1213H)
ML-KEM-512/768/1024 (CRYSTALS-Kyber), Balanced (XIP6110B)

IP Core

ML-KEM-512/768/1024 (CRYSTALS-Kyber), Balanced (XIP6110B)

ML-KEM-512/768/1024 is an IP core for post-quantum Key Encapsulation Mechanism (KEM), optimized for a good balance between speed and resource requirements.
ML-KEM-512/768/1024 (CRYSTALS-Kyber), Balanced (XIP6110B)

Development Kits & Boards

Avant-E Evaluation Board

Board

Avant-E Evaluation Board

The Avant-E Evaluation Board has the ability to expand the usability of the Avant-E FPGA with FMC HPC, PMOD, and Raspberry PI connectors.
Avant-E Evaluation Board
Avant-X Versa Board

Board

Avant-X Versa Board

Avant-X Versa Board support devices that offers a modernized feature set for accelerated system design and fastest soft error detect (SED).
Avant-X Versa Board
Lattice Sentry 4.0 Demo Board for MachXO5D-NX

Board

Lattice Sentry 4.0 Demo Board for MachXO5D-NX

A complete platform to help you develop and test a NIST 800-193-compliant PFR solution and help in SoC project in Lattice Radiant and Propel 2024.1 Tools.
Lattice Sentry 4.0 Demo Board for MachXO5D-NX
Lattice Sentry Demo Board for Mach-NX

Board

Lattice Sentry Demo Board for Mach-NX

A complete platform to help you develop and test a NIST 800-193-compliant PFR solution. Includes numerous features to enable debug, interface and expansion
Lattice Sentry Demo Board for Mach-NX
CrossLink-NX Evaluation Board

Board

CrossLink-NX Evaluation Board

For general evaluation and development with CrossLink-NX, includes many flexible interfaces such as FMC and PMOD with generous device IO access
CrossLink-NX Evaluation Board

Demos

Demo for Lattice ORAN Secure Sync for IEEE 1588 PTP

Demo

Demo for Lattice ORAN Secure Sync for IEEE 1588 PTP

Demo for Lattice ORAN Secure Sync show how Lattice FPGA w/ soft IPs can support tight & secure synchronization using 1588 PTP & ITU profiles for Telecom.
Demo for Lattice ORAN Secure Sync for IEEE 1588 PTP

Quality Programs

Lattice is committed to Industry Leadership in the supply of high quality programmable logic components and software design tools.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-02076 2.3 10/13/2025 PDF 806.2 KB
Single Event Upset (SEU) Report for Nexus Platform
FPGA-TN-02174 1.8 10/13/2025 PDF 453.7 KB
Implementing JOTP-051-Compliant Safety Features in Lattice FPGAs
FPGA-TN-02150 1.1 3/15/2021 PDF 855.2 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Lattice Defense-Grade FPGA Portfolio
SB006 1.0 1/7/2026 PDF 2.1 MB
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-02076 2.3 10/13/2025 PDF 806.2 KB
Single Event Upset (SEU) Report for Nexus Platform
FPGA-TN-02174 1.8 10/13/2025 PDF 453.7 KB
Implementing JOTP-051-Compliant Safety Features in Lattice FPGAs
FPGA-TN-02150 1.1 3/15/2021 PDF 855.2 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Lattice Defense-Grade FPGA Portfolio
SB006 1.0 1/7/2026 PDF 2.1 MB
Defense Solutions Brief
I0271 Rev 1 8/4/2020 PDF 1.6 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Nexus SEU White Paper
1.0 8/12/2025 PDF 87.9 KB
A Guide to the Benefits of the Lattice Nexus FPGA Platform for Mission-Critical Applications
WP0028 1.0 1/22/2021 PDF 449.4 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

Support

Technical Support

Need Help? We're Here to Assist You

Quality & Reliability

Reference Material to Help Answer Your Questions