可编程逻辑(FPGA、 CPLD…)

Intefacing_with_SPI_Devices_Part_2

Interfacing with SPI Devices, Part 2

Posted 09/23/2021 by Eugen Krassin

This blog post focuses on how to implement a clock domain SPI interface between a DAC and a Lattice FPGA.

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Memory_Flexibility_Blog_Image

Memory Flexibility Key to FPGA-Based Designs

Posted 09/13/2021 by Bob O'Donnell

Combining Micron LPDDR4 memory with Lattice FPGAs can enable Edge applications with low power consumption and strong performance characteristics.

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Interfacing with SPI Devices, Part 1

Interfacing with SPI Devices, Part 1

Posted 09/07/2021 by Eugen Krassin

This blog post focuses on how to implement a two clock domain SPI interface between a DAC and a Lattice FPGA.

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Lattice Certus-NX FPGAs Optimized for Automotive Applications

专为汽车应用优化的莱迪思Certus-NX FPGA

Posted 08/25/2021 by Juju Joyce

莱迪思Certus-NX通用FPGA系列现提供通过AEC-Q100认证的汽车级产品,可广泛应用于各类汽车应用。

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Redefining the FPGA for Aerospace and Defense by Solving SWaP-C Challenges

Redefining the FPGA for Aerospace and Defense by Solving SWaP-C Challenges

Posted 08/24/2021 by Luke Miller

Learn how FPGAs can help address size, weight, power, and cost challenges for aerospace and defense applications.

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Cyber Security Trends and Standards in Automotive FPGAs

汽车FPGA的网络安全趋势和标准

Posted 07/06/2021 by Eric Sivertson

在主题为《汽车FPGA的网络安全趋势和标准》的线上研讨会中,莱迪思半导体重点介绍了汽车应用中的莱迪思FPGA在全球供应链中运输时,OEM厂商如何保护它们免受网络攻击。

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Say Hello to CertusPro-NX General Purpose FPGAs

CertusPro-NX通用FPGA面世

Posted 06/23/2021 by Juju Joyce

莱迪思CertusPro-NX FPGA在数据处理性能、系统带宽、存储密度和支持器件小尺寸方面远超过同类FPGA。

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Lattice Partners with Defense Customers to Ensure Mission Critical Longevity

Lattice Partners with Defense Customers to Ensure Mission Critical Longevity

Posted 06/15/2021 by Luke Miller, Vice President, Aerospace & Defense Business Development

Lattice is committed to helping our customers in the defense market to ensure they have the support they need to keep legacy defense systems available after components are discontinued.

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The Importance of Timing Constraints in FPGA Designs

FPGA设计中时序约束的重要性

Posted 06/07/2021 by Eugen Krassin

这篇博文重点介绍了如何在莱迪思FPGA上合理地说明和验证时序约束。

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Want Embedded Vision? Got MIPI?

莱迪思在2021年嵌入式视觉峰会上展示灵活的AI/ML开发并发布sensAI 4.0

Posted 05/25/2021 by Sreepada Hegade

屡获殊荣的Lattice sensAI解决方案集合4.0版本的增强特性包括支持Lattice Propel设计环境和Lattice sensAI Studio设计环境,实现端到端的ML模型训练、验证和编译。

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