Lattice Blog

Read the latest comms and computing news from Lattice: Low power wireless Heterogenous Networks development and upgrade security with Lattice’s MachXO3D FPGA.

We live in an increasingly connected world, filled with communication systems, cloud computing and Edge devices working together to increase safety, comfort and convenience. But with that connectivity comes risk. We’re all familiar with how hackers exploit vulnerabilities in software to illegitimately access systems, but hardware is also vulnerable.

A key benefit of programmable logic devices, such as FPGAs and CPLDs, is their programmability. These devices are typically deployed with a unique design intended to address application-specific problems. And because of these problems, many embedded systems that deploy programmable products benefit greatly from the ability to update their design and configuration after manufacturing. An upgrade feature is useful for multiple end-applications.

In this 6 part series we are looking at the challenges of implementing an efficient power management architecture in today’s complex circuit board designs.

In our 5^th post, we will look at one final attempt to develop an efficient power management solution for a modern circuit board. In this model we have come full circle. The control PLD is back in charge of all power management functions.

Our previous post covered a hybrid architecture, where the control PLD was splitting the power management responsibilities with a dedicated power manager IC. This next option is used by some designs to replace the dedicated power manager IC with a software driven MCU.

In our last post, we looked at an architecture where the control PLD controlled all of the power management functionality and identified any weaknesses around congestion and crosstalk. Today, we will review a hybrid architecture that attempts to solve the congestion/crosstalk problems by ...

In this 6-part series, we are looking at the challenges of implementing an efficient power management architecture in today’s complex circuit board designs.

The consumer’s desire for new technology is insatiable. To meet this demand, engineers are constantly striving to make things smaller, faster, cheaper, and better. As sizes shrink and complexity increases, we often find that techniques that have served us well for a long time no longer meet our needs. We must evolve alongside our designs.

Today’s designers face a major challenge: How do I pack more functionality into a board, and do it faster and cheaper? The go-to approach to solving this problem is to implement data path or payload functions using highly integrated ASICs and SoCs. However, the design is not complete by simply connecting all the large devices together.