Power Management Using a Power Manager IC and Control PLD

In this 6 part series we are looking at the challenges of implementing an efficient power management architecture in today’s complex circuit board designs.

In our last post, we looked at an architecture where the control PLD controlled all of the power management functionality and identified any weaknesses around congestion and crosstalk. Today, we will review a hybrid architecture that attempts to solve the congestion/crosstalk problems by splitting the power management responsibilities between the control PLD and a dedicated power manager IC.

In this hybrid architecture, the control PLD continues to monitor “Power Good” and generates necessary control, status and housekeeping signals, while a dedicated power manager IC is responsible for monitoring and sequencing of the board's DC-DC converters (see image below). The power manager functionality is typically defined using GUI-based configuration tools, while the control PLD logic is defined using VHDL or Verilog.

A Hardware Management System Implemented Using
Power Manager ICs and a Control PLD

Pros:

• Lower Control PLD I/O count due to power manger “Enable” function handling.
• Lower board congestion leads to simpler layout and fewer board layers.
• Direct monitoring of the supply voltages, for a more accurate system health diagnosis and reliability.

Cons:

• Increased BOM cost – especially if multiple power manager devices are required.
• Deployment of more than one power manager IC can increase design complexity.
• Sequencing for complex designs can be difficult – especially during partitioning functionality across multiple power managers.
• Multiple tools (GUI + VHDL/Verilog) may require support from multiple engineers.

While this design eliminates the board congestion issue, it comes at the expense of increased BOM cost and complexity. Multiple power manager ICs may be needed to cover all the supplies on the board. In such cases power manager devices must communicate between each other to respond to supply faults in a uniform manner. Further, implementing sequencing in a multi-power manager IC designs requires that the sequencing algorithm be partitioned. This, coupled with multi-power manager-chip communication and implementation of event-based fault response, complicates sequencing algorithm further.

How can we eliminate this additional complexity? By exploring another architecture in our next blog.

Read other blogs from our Power Manager series:

• The Quest for the Optimal Power Management Architecture
• Power Management with a Control PLD

Click on the links to learn more about our power manager products and development kits and boards.