Lattice Blog


Simplify board design and debug with Control PLDs

Simplify board design and debug with Control PLDs
Posted 05/10/2016 by Shyam Chandra

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Today’s designers face a major challenge: How do I pack more functionality into a board, and do it faster and cheaper? The go-to approach to solving this problem is to implement data path or payload functions using highly integrated ASICs and SoCs. However, the design is not complete by simply connecting all the large devices together. Additional control path functions such as Power Management, level translation bridging functions, board specific glue logic, serial ports and I/O expansion may be needed. And the most convenient way to implement all these control path functions is to integrate them onto a single, programmable device such as a CPLD or a non-volatile FPGA – called the control PLD.

Tell me more about CLPDs & non-volatile FPGAs

CPLDs and non-volatile FPGAs are known for their flexibility to quickly and inexpensively integrate all control path functions. A Control PLD is usually the first device to be turned on in a system and the last device to turn off after shutting all other components in an orderly manner. While I/Os are almost always finalized during the early stages of design, the logic implemented within the control PLDs usually changes throughout the design and debug cycles. Designers can freely add more logic for a given footprint. If a device’s logic utilization exceeds the device’s capacity, the designs can be migrated to a device with a higher logic density (density shifting). And even after the board is deployed in the field, these devices give the user the option to modify the designs without having to bring the board back to the factory.

Sometimes, increased logic capacity or I/Os may not be enough. Applications like video bridging need more internal memory along with improved logic support to increase on-chip image buffering for improved image sharpness in large monitors. Another example is designs using an integrated soft processor, where internal code size might exceed the on-chip resources during design and debugging. To accommodate such increased resource demands, CPLDs and non-volatile FPGAs are required to support more embedded on-chip memory.

Ready for a non-volatile FPGA that is also a CPLD?

Our MachXO3 devices offer a wide range of density, I/O features, and packages to cover a spectrum of control PLD applications that require a CPLD to non-volatile FPGA. Enhanced features of these devices enable them to meet the control PLD demands of modern day complex systems. The recently added MachXO3L-9400 and MachXO3LF-9400 devices with 384 I/Os, 9400 LUTs and almost 0.5Mb of embedded RAM were created in direct response to feedback from our customers who loved the flexibility of the MachX03 family, but were looking for more I/Os and an even more cost efficient package. These new devices are ideal for the server, communications, industrial and display markets and will simplify the use of the most advanced components while staying on budget and on time. Low end of the MachXO3 family of devices bring higher end features into CPLD devices. Now even the simpler systems can benefit by higher end non-volatile FPGA features.

As the boards become more complex, the logic, performance and number of I/Os will need to keep up. And with the expanded family and features of our Lattice MachXO3 line, you, the designers, will be ready to take on the challenge.