Advanced Secure Control FPGA

MachXO5-NX is Lattice’s secure control FPGA product family. Known for features such as embedded flash, high I/O, and best-in-class security, Lattice’s secure control FPGAs are widely used for system control and management applications in the Compute, Communications, and Industrial market segments. MachXO5-NX improves upon previous generations with higher logic density, faster interfaces, larger internal memory, and enhanced security features enabling more complex board management designs.

Higher Density, More Memory for Complex Control Applications – Up to 100K logic density, 7.3Mb internal memory , and 55Mb dedicated user flash memory (UFM).

Fast and Proven I/O Capabilities – Consistent robust I/O operation as previous generation, 1.0V I/O supporting modern CPU, high speed LVDS, MIPI and PCIe interfaces.

Device Security Protects Intellectual Property – Internal flash configuration, AES256 bitstream encryption, ECC256 bitstream authentication, configuration port lock, and run-time security


  • 25K, 55K, and 100K logic cell density and up to 299 I/O pins
  • MachXO5T devices (55K and 100K LC) support PCIe Gen2.
  • Up to 55 Mbits of dedicated user flash memory (UFM) and on-chip multi-boot configuration
  • Secure FPGA design using ECDSA bitstream authentication and AES256 encryption
  • Low power, high reliability, and support for ADC and DSP on the Lattice Nexus™ Platform

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Family Table

MachXO5-NX Device Selection Guide
Features MachXO5-NX MachXO5T-NX
Devices LFMXO5-25 LFMXO5-55T LFMXO5-100T
Logic Cells
53k 96k
Embedded Memory (EBR) Blocks (18 kb) 80 166 208
Embedded Memory (EBR) Bits (kb) 1440 2988 3744
Distributed RAM Bits (kb) 184 320 639
Large Memory (LRAM) Blocks 1 5 7
Large Memory (LRAM) Bits (kb) 512 2560 3584
18 X 18 Multipliers 20 146 156
ADC Blocks 2 2 2
450 MHz High Frequency Oscillator 1 1 1
128 kHz Low Power Oscillator 1 1 1
PCIe Gen2 hard IP 0 1 1
GPLL 2 4 4
UFM* (kb) 15360 79872 79872
0.8 mm Pitch Packages & SERDES / Total I/O (Wide Range GPIO / High Performance GPIOs) / Dedicated ADC pins

256 BBG (14 mm × 14 mm, 0.8 mm) 0 / 199 (159/40) / 6 - -
400 BBG (17 mm × 17 mm, 0.8 mm) 0 / 299 (251/48) / 6 2 / 291 (159/132) / 6 2 / 291 (159/132) / 6

*Without memory initialization

Block Diagram


  • Up to 100K logic cells, 7.3Mb embedded memory , and 55Mb dedicated user flash memory (UFM)
  • MachXO5T devices (55K & 100K LC) support PCIe Gen2 and LPDDR4
  • Up to 299 programmable I/O supporting 1.0/1.2/1.5/1.8/2.5/3.3 I/O voltages
  • Protects intellectual property with bitstream encryption and authentication

Example Applications

Application – Network Switch

  • Aggregates control signals over PCIe
  • Offload real-time monitoring and management of SFPs from network CPU

Application – Hardware Management

  • Easily integrate hardware management functions into MachXO5-NX and L-ASC10
  • High I/O and multiple voltage level support simplify I/O bridging and expansion

Application – LVDS Tunneling Protocol & Interface (LTPI) in Datacenter-ready Secure Control Module

  • Supports LVDS Tunneling Protocol & Interface (LTPI) to aggregate low-speed serial interfaces
  • Enables server architecture that uses secure control modules
  • LTPI is also supported by MachXO3, MachXO3D and Mach-NX

Design Resources

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Intellectual Property & Reference Designs

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